How to synthesize a delay of around 10 ns in FPGA?

On Oct 20, 8:49=A0pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On Oct 20, 3:30=A0pm, Pratap <pratap.i...@gmail.com> wrote:
>
>
>
> > On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com>
> > wrote:> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:
> > > > Hi,
> > > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro.=
 So I
> > > > put around 200 inverters in series and get the desired delay. So I =
did
> > > > port map the BASIC cell "INV" according to the XST settings. But wh=
en i
> > > > place and route I guess the optimizer removes all the intermediate
> > > > buffers and I get very less delay when I do a post route simulation=
.
> > > > How can I get rid of this problem?
>
> > Hi,
> > Can you please send me some good material on DCM?
> > I actually require to generating delays around 0 ps by having a
> > passive
> > delay of around 1 period and then increasing and decreasing the input
> > frequency slightly.Can DCM help me in that case?
> > -pratap
>
> > > > Thanks in advance.
> > > > -Pratap
>
> > > Do you need a delay or can you accomplish your task with a phase shif=
ted
> > > clock? If you can use a phase shifted clock from the DCM that's a muc=
h
> > > better way of doing it because it's stable over temperature and proce=
ss
> > > and because it won't change when the tools change.
>
> > > If you must build a delay line from buffers you will have to directly
> > > place them because the routing delays are much more important then th=
e LUT
> > > delays. Also you should use an XOR instead of an inverter. Tie one si=
de of
> > > the XOR to a flop which presets to 1 on reset and then clocks a zero =
into
> > > the data input. This will be enough to fool XST and PAR into leaving =
the
> > > components alone.
>
> The important question is: Who decides when to start your delay.
> If you can wait until an oscillator has a rising edge, then there are
> many high-quality solutions, especially when you know the delay value
> well beforehand. With the help of frequency synthesis and PLLs, you
> can generate a delay with very fine resolution, even below a
> picosecond. (Of course you lose that accuracy as you propagate through
> more logic.)
> If, however, you need to be the master of starting the delay, then you
> are much more constrained, and your best bet is what Virtex-4 and
> later did by cascading analog delay elements, and servo-controlling
> their composite delay. And the inherent accuracy will be not perfect,
> with an error of a nanosecond, unless you get really creative.
> Peter Alfke, lurking from home...

Hi,
I read the manual of Virtex2P for the DCM.But I found it not useful
for me.
All I require is a fixed delay of around 10ns.The precision doesn't
matter.But it has to be stable.Then if I feed a square wave of say
10ns period.I get the effective delay between the original and the
delayed signal as 0 ps. If I increase the input period to 10.001ps, I
get the delay to be 1ps and similarly for an input period of 9.999ns I
get a delay of -1ps. So all I require here is a fixed constant delay
like that of a passive element.
When I synthesize a bunch of cascaded even number of inverters, I get
the synthesized technology schematic as expected too.Even after the
"translate" phase it i in tact. But after the "map" phase many signals
disappear.I guess it does some optimization in this step and removes
all the intermediate signals and delays.is there any way to tell the
mapper not to optimize?
Thanks,
Pratap

Pratap wrote:
>
> Hi,
> I read the manual of Virtex2P for the DCM.But I found it not useful
> for me.
> All I require is a fixed delay of around 10ns.The precision doesn't
> matter.But it has to be stable.Then if I feed a square wave of say
> 10ns period.I get the effective delay between the original and the
> delayed signal as 0 ps. If I increase the input period to 10.001ps, I
> get the delay to be 1ps and similarly for an input period of 9.999ns I
> get a delay of -1ps. So all I require here is a fixed constant delay
> like that of a passive element.
> When I synthesize a bunch of cascaded even number of inverters, I get
> the synthesized technology schematic as expected too.Even after the
> "translate" phase it i in tact. But after the "map" phase many signals
> disappear.I guess it does some optimization in this step and removes
> all the intermediate signals and delays.is there any way to tell the
> mapper not to optimize?
> Thanks,
> Pratap

You will not get a super-stable delay in an FPGA because these devices
are not designed as timing elements but instead are intended to
provide extreme functionality.

If you implement a series of inverters with LUT primitives (which
should not get optimized out) you still end up with differences due to
global or local temperature changes on the die and due to local
activity in the form of minute changes in the voltage rail or coupled
energy from other nearby activity that are fine in the digital world.
The analog world of transition thresholds are a different matter.

If you need picosecond level consistency, develop a discrete analog or
analog/digital hybrid solution to achieve your goals.  You will need
to pay special attention to power and to electromagnetic coupling and
either need a very well behaved feedback loop to keep the delay solid
to the picosecond level or you'll need to regulate the temperature of
the circuit (such as with ovenized oscillators) and maintain a smooth
power consumption.

I've implemented delay elements in an FPGA but I've been allowed more
slop and performed my own adjustments to the 100 ps (or smaller) level
using carry chain elements directly feeding a series of registers.
It's not a variable delay to another part of the circuit and it's
certainly 2 orders of magnitude (base 10) from the picosecond level of
control you're asking for.  The delay maintenance is not a simple
task, introduces jitter, and shows signs of "swaying" back and forth
under normal operation.

Go analog.  Or figure out what you really need, not just what you
dream up.

- John_H

If you really want a fixed delay using internal FPGA resources, I suggest
making a hard macro (.nmc file) using the "fpga_editor" command.  You can
hand route it in fpga_editor and see what delays you are getting.  It's not
too hard to do (after the first time) and you get to see at a very low level
how Xilinx FPGAs work.

This is not a compensated delay, so it will vary as the FPGA heats up, but
it will be stable over short times.  Also expect jitter from other logic in
the fpga and ground bounce on the external pins.  If you care about ps
jitter, use differential I/O and/or have nothing else in the FPGA.

Next option is one my favorite class of chips: time delay vernier chips such
as SY604.

Next is get a different FPGA, either newer Virtex-4 (IDELAY, 5 ns max) or
Startix-3/Cyclone-3 (altiobuf, 1.1 ns max) which have compensated variable
delay lines in their I/O pads.  The way to make these work is to feed your
clock into two otherwise identical chains of delays, with one set to zero
and the other to 10 ns.  Then use the 0 delay one as your new undelayed
clock.  This removes the effects of the uncompensated routing delays.  Still
this will be difficult to implement, since you want the tool to always
generate a consistent routing delay, which is hard to do.

I don't know about Xilinx, but you can ask for min and max routing delays
from pin to pin with Altera's TimeQuest.  So a final easy thing to try is
use put a bunch of multi-input xor gates in series and try to constrain
them.  Tie the unused inputs of the xor gates to separate input pins to
prevent the tool from optimizing them out (it doesn't know that you are
going to tie them all high externally).
-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

> But it has to be stable.Then if I feed a square wave of say
> 10ns period.
Do you allways have periodic signals? That is a completely different
story than random signal. If you want to phase shift a periodic signal
you can use delay locked loops or phase locked loops.

I get the effective delay between the original and the
> delayed signal as 0 ps. If I increase the input period to 10.001ps, I
> get the delay to be 1ps and similarly for an input period of 9.999ns I
> get a delay of -1ps. So all I require here is a fixed constant delay
> like that of a passive element.

Any signal inside an FPGA will have more than 100ps jitter. All you
can hope
for is an average delay resolution in that order.
Even with specialized discrete analog hardware it is hard to get into
the range of 1ps jitter even for clock signals let alone for logic.

Kolja Sulimma
www.cronologic.de

On Oct 24, 12:24=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> > But it has to be stable.Then if I feed a square wave of say
> > 10ns period.
>
> Do you allways have periodic signals? That is a completely different
> story than random signal. If you want to phase shift a periodic signal
> you can use delay locked loops or phase locked loops.
>
> I get the effective delay between the original and the
>
> > delayed signal as 0 ps. If I increase the input period to 10.001ps, I
> > get the delay to be 1ps and similarly for an input period of 9.999ns I
> > get a delay of -1ps. So all I require here is a fixed constant delay
> > like that of a passive element.
>
> Any signal inside an FPGA will have more than 100ps jitter. All you
> can hope
> for is an average delay resolution in that order.
> Even with specialized discrete analog hardware it is hard to get into
> the range of 1ps jitter even for clock signals let alone for logic.
>
> Kolja Sulimmawww.cronologic.de

I  am actually not interested in instantaneous delay(jitter)...all I
want is the average delay over a period of time to be constant.
Finally I was able to get the delay...
I had to tell the mapper not to touch the intermediate signals and not
to eliminate the buffers by using the statement like this....Now it
synthesizes each and every inverter and I get the delay I
require... :-)
.
.
.
signal inv1 :	STD_LOGIC;
attribute s: string;
attribute s of inv1: signal is "yes";
A0 : INV port map(inv1,core_clk);
.
.
.
Thanks,
Pratap

Pratap wrote:
> 
> I  am actually not interested in instantaneous delay(jitter)...all I
> want is the average delay over a period of time to be constant.
> Finally I was able to get the delay...
> I had to tell the mapper not to touch the intermediate signals and not
> to eliminate the buffers by using the statement like this....Now it
> synthesizes each and every inverter and I get the delay I
> require... :-)
> .
> .
> .
> signal inv1 :	STD_LOGIC;
> attribute s: string;
> attribute s of inv1: signal is "yes";
> A0 : INV port map(inv1,core_clk);
> .
> .
> .
> Thanks,
> Pratap

THis delay has absolutely none of the requirements you asked for.  You 
do not have 1ps class resolution.  The stability is not there with 
temperature and local activity affecting your overall delay by as much 
as 10%.

Part of the art of getting useful information from a pool of experienced 
individuals on a newsgroup is asking the right question!