A couple of CPLD design challenges for the group

The purpose of this post is to try to get a discussion going
on various design tricks for severely limited devices like CPLDs.
On that note I'll pose the following challenges to the group:



Challenge 1 - Tetris in as few CPLDs as possible
------------------------------------------------

How would you design a Tetris game if you only had CPLDs
available? How many CPLDs would you use and of what kind?

Would you need any other kind of circuits to implement an
efficient solution? (External SRAMs or EPROMs for example?)

What kind of display would you use? (TV, Oscilloscope, Led matrix, etc?)
What kind of input device would you use? (Plain buttons or perhaps a
more advanced input device like a NES joypad?)


I believe that this is a rather nice problem with many
interesting optimization possibilities.


Personally I have an almost finished solution based on the XC95 series.
However, I will not tell you how many I need or the exact model number(s)
that I'm using right now. I do have a rather nice architecture which I
believe will be hard to improve on. I'll let you ponder this for a week
or so before I post my idea for a solution.




Challenge 2 - A digital watch with as few CPLDs as possible
-----------------------------------------------------------

This is an easier problem which should require fewer or smaller CPLDs
than the previous challenge.

Requirements:
* Time should be showed in HH:MM:SS format (preferably 24h format)
* It should be possible to set an alarm (HH:MM precision is good enough)
* Stop watch functionality in MM:SS:T   (That is, up to 59 minutes, 59
  seconds and 9 tenths of a second.)
* There should be a user interface of some kind (it should be possible to
  change the time that is)
* The time, alarm, and stop watch functionality shall work independently.
  (You don't want your watch to stop working just because you are setting
  your alarm or using the stop watch.)


What kind of display would you use here? (7 segment LEDs? LCD?, etc?)
What kind of input? (Plain buttons or something different?)
What clock frequency do you need?

This is a rather nice problem which will allow you to think about the
best way to do resource sharing in a CPLD.

As a baseline, the students I have supervised who do this kind of project
end up with about 3 or 4 CPLDs. (Either XC9572 or XC95108.) They usually
don't bother with any kind of resource sharing though...


Personally, I have a relatively small solution to this, but there are still
a few tricks I haven't used. In my solution I'm using a 7 segment LED driver
circuit with built in NBCD decoder (the 9368), so if you want to compare
your solution to mine you might want to output NBCD coded numbers out of your
CPLD.

I'll let you ponder this problem for a few days or so as well before
doing a small writeup on my solution.


/Andreas

On 2008-10-16, Herbert Kleebauer <klee@unibwm.de> wrote:
> Andreas Ehliar wrote:
>> 
>> The purpose of this post is to try to get a discussion going
>> on various design tricks for severely limited devices like CPLDs.
>> On that note I'll pose the following challenges to the group:
>> 
>> Challenge 1 - Tetris in as few CPLDs as possible
>  
>> Challenge 2 - A digital watch with as few CPLDs as possible
>
> Put a simple soft core CPU in a xc95 and add some ROM/RAM, then
> a single CPLD should be enough.

That is probably the easiest solution. A colleague and I have
investigated this approach a little bit to try to figure out the
optimal architecture. The goal would be to have both sound output
and tile based graphics in this case. We were aiming for a XC9572,
but we gave up on it since programming would be extremely cumbersome
as both audio and video would require cycle accurate code.

Some of the tricks we learned while doing this was to move around
our address register and the program counter so that one of them
always addressed the memory.

At first we considered the following architecture:

       +---+
PC --->|   |
       |MUX|---> Address to memory
AR --->|   |
       +---+

However, if we do it like this instead:

 +-------------------------------+
 |                               |
 |  +--+                 +--+    |
 |  |PC|    +-------+    |AR|    |
 +->|  |--->| Adder |--->|  |----+---> Address to memory
    |> |    +-------+    |> |
    +--+                 +--+

The adder adds either 1 or 0. If we always exchange PC and
AR two times during the execution of one instruction we will
both be able to address memory through the address register and
fetch the instruction. We will also get the operation AR++ for
free. But most importantly: As we no longer have the mux, we save
these macrocells for other uses. This is quite important since the 9572
only has 72 macrocells...


However, what about if you would like to avoid an SRAM and EPROM,
what kind of techniques would you use in that case?

/Andreas

On 2008-10-16, Frank Buss <fb@frank-buss.de> wrote:
> Andreas Ehliar wrote:
>
>> How would you design a Tetris game if you only had CPLDs
>> available? How many CPLDs would you use and of what kind?
>
> The question doesn't make sense. I would use a EPM2210/G with 2,210 LEs and
> could install Nios on it, so all I need is one CPLD.

My intention was to challenge the group to use as few CPLDs
and as small CPLDs as possible.

Although I admit that you will be probably be finished with
your solution before I'm even finished with trying to figure
out the architecture of my solution :)

/Andreas

On 2008-10-16, Jim Granville <no.spam@designtools.maps.co.nz> wrote:
> No mention of leading zero suppression ?

I haven't really thought about it, but that would make a nice addition :)

>> What kind of display would you use here? (7 segment LEDs? LCD?, etc?)
>
> MUX'd or Non MUX'd ?
> LCDs need a XOR backplane, and they also have MUX choices too.

I didn't use a mux'd solution, but as you point out further down I'm
cheating somewhat with my choice of LED drivers. MUX'd would probably
be better if using traditional driver circuits like the ULN2003.

> 50Hz, 60Hz and 32.768KHz are the common ones....

50 Hz and 60 Hz are quite hard if you want to do some kind of resource sharing.
If you use 32768 Hz it is much easier to move things around to only one
arithmetic block.

> You could get them to code direct 7 segment counters, for a non-mux 
> display. Nice to show there are non Bin/bcd counters possible too...

I haven't thought about that at all, that is a very interesting counter idea.
It is probably not going to be useful in many cases but you never know when
something similar will save your day :)


>> Personally, I have a relatively small solution to this, but there are still
>> a few tricks I haven't used. In my solution I'm using a 7 segment LED driver
>> circuit with built in NBCD decoder (the 9368), so if you want to compare
>> your solution to mine you might want to output NBCD coded numbers out of your
>> CPLD.
>
> Surely the 9368 should be part of the CPLD ?

Yes. But I had to use some sort of LED driving circuit, and we had lots of 9368
in the lab :) Perhaps I'll try to update my solution to use a more traditional
LED driver instead. Unfortunately that is probably going to mean that I have to
use a larger CPLD as the current version is filled to the limit. On the other
hand, that would also allow me to fit a clock prescaler into the CPLD to avoid
the very non-standard frequency the current solution needs :)

But I agree that I'm cheating a little bit here.

/Andreas

On 2008-10-16, Jim Granville <no.spam@designtools.maps.co.nz> wrote:
> A nice small device for this, would be the new Serial SPI SRAM ?
> http://www.onsemi.com/PowerSolutions/parametrics.do?id=2207
> SO8 or tssop8.

This kind of device could be rather nice in some situations, thanks
for mentioning it. It was fairly affordable on digi-key as well although
not extremely cheap.

> Perhaps add a SPI flash memory for the tiles
> (quite large flash comes now in SO8, so I'd load one up with thousands
> of next-tiles, and shift the random-tile decisons to the 
> flash-generation code :) - keeps the CPLD simpler...

Nice idea. Although I must admit that my current solution doesn't really
use any sort of tiles at all, just fully white or fully black (large)
pixels.

> all that assumes you stay in macrocell CPLDs, and do not move to
> a Lattice MachXO type device.

Exactly, this isn't very challenging in such a device, especially the
ones with built in block rams. I've looked into the MachXO devices a
little bit (I supervised a final year project which used such a device)
and they seem like rather nice devices. If you are used to optimizing
CPLD designs for the limitations of a traditional CPLD, the MachXO is
luxuriously large... :)

/AE

Andreas Ehliar wrote:
> 
> The purpose of this post is to try to get a discussion going
> on various design tricks for severely limited devices like CPLDs.
> On that note I'll pose the following challenges to the group:
> 
> Challenge 1 - Tetris in as few CPLDs as possible
 
> Challenge 2 - A digital watch with as few CPLDs as possible

Put a simple soft core CPU in a xc95 and add some ROM/RAM, then
a single CPLD should be enough.

Andreas Ehliar wrote:

> How would you design a Tetris game if you only had CPLDs
> available? How many CPLDs would you use and of what kind?

The question doesn't make sense. I would use a EPM2210/G with 2,210 LEs and
could install Nios on it, so all I need is one CPLD.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Andreas Ehliar wrote:

> Challenge 2 - A digital watch with as few CPLDs as possible
> -----------------------------------------------------------
> 
> This is an easier problem which should require fewer or smaller CPLDs
> than the previous challenge.
> 
> Requirements:
> * Time should be showed in HH:MM:SS format (preferably 24h format)
> * It should be possible to set an alarm (HH:MM precision is good enough)
> * Stop watch functionality in MM:SS:T   (That is, up to 59 minutes, 59
>   seconds and 9 tenths of a second.)

Why stop at :T, push the students a little :)
ask for :TT - easy at 50Hz AC, a little harder at 60Hz and 32.768KHz
- or even :TTT, and make a precision sports timer, with optical gates.

Pass that to the Physics teachers and sports teams...


> * There should be a user interface of some kind (it should be possible to
>   change the time that is)
> * The time, alarm, and stop watch functionality shall work independently.
>   (You don't want your watch to stop working just because you are setting
>   your alarm or using the stop watch.)

No mention of leading zero suppression ?

> 
> What kind of display would you use here? (7 segment LEDs? LCD?, etc?)

MUX'd or Non MUX'd ?
LCDs need a XOR backplane, and they also have MUX choices too.

> What kind of input? (Plain buttons or something different?)

This opens up a large range of complexity/user-friendly trade offs:
Up/Dn buttons are more friendly, but make more complex counters.
Rotary encoders are even nicer, and a rate-sensistive rotary encoder
nicer still.

> What clock frequency do you need?

50Hz, 60Hz and 32.768KHz are the common ones....

> 
> This is a rather nice problem which will allow you to think about the
> best way to do resource sharing in a CPLD.
> 
> As a baseline, the students I have supervised who do this kind of project
> end up with about 3 or 4 CPLDs. (Either XC9572 or XC95108.) They usually
> don't bother with any kind of resource sharing though...

You could get them to code direct 7 segment counters, for a non-mux 
display. Nice to show there are non Bin/bcd counters possible too...

> Personally, I have a relatively small solution to this, but there are still
> a few tricks I haven't used. In my solution I'm using a 7 segment LED driver
> circuit with built in NBCD decoder (the 9368), so if you want to compare
> your solution to mine you might want to output NBCD coded numbers out of your
> CPLD.

Surely the 9368 should be part of the CPLD ?

-jg

Andreas Ehliar wrote:

> The purpose of this post is to try to get a discussion going
> on various design tricks for severely limited devices like CPLDs.
> On that note I'll pose the following challenges to the group:
> 
> 
> 
> Challenge 1 - Tetris in as few CPLDs as possible
> ------------------------------------------------
> 
> How would you design a Tetris game if you only had CPLDs
> available? How many CPLDs would you use and of what kind?
> 
> Would you need any other kind of circuits to implement an
> efficient solution? (External SRAMs or EPROMs for example?)

You need to define the Pixels and tile-sets.

A nice small device for this, would be the new Serial SPI SRAM ?
http://www.onsemi.com/PowerSolutions/parametrics.do?id=2207
SO8 or tssop8.

Perhaps add a SPI flash memory for the tiles
(quite large flash comes now in SO8, so I'd load one up with thousands
of next-tiles, and shift the random-tile decisons to the 
flash-generation code :) - keeps the CPLD simpler...

all that assumes you stay in macrocell CPLDs, and do not move to
a Lattice MachXO type device.

> 
> What kind of display would you use? (TV, Oscilloscope, Led matrix, etc?)

Depends on the desired resolution. LED matrix is going to be a bit coarse.
TV is the most widely available.  (PAL or NTSC)

> What kind of input device would you use? (Plain buttons or perhaps a
> more advanced input device like a NES joypad?)

Rotary encoder perhaps ?

-jg

Andreas Ehliar wrote:
> On 2008-10-16, Herbert Kleebauer <klee@unibwm.de> wrote:

> > Put a simple soft core CPU in a xc95 and add some ROM/RAM, then
> > a single CPLD should be enough.
> 
> That is probably the easiest solution. A colleague and I have
 
> However, what about if you would like to avoid an SRAM and EPROM,
> what kind of techniques would you use in that case?

I would use a FPGA instead of CPLD. With a xc3s1200e you can use 
32 kbyte internal program/data memory an then have all the IO pins
available for other purpose and with a simple CPU you also have
nearly all the logic in the FPGA available for additional hardware.
Here a CPU which uses 72 of 17344 Slice Flip Flops and 142 of
17344 4 input LUT's of xc3s1200e-4fg400.

ftp://137.193.64.130/pub/mproz/mproz3_e.pdf