Learning WinCUPL; Tried Atmel Suppport but no solution!

I am fairly new to CPL development, and I need to create an emulation
of a number of old bipolar Proms (256x4) being used in a very old
system by using a CPLD and WInCUPL.

My approach was to use the example "Lookup.pld" as a basis for my LUT,
with the exception that I am trying to use 8 bits of address to
produce a 4 bit output for each of the possible 256 inputs.

Using an AT22V10, I am able to (sometimes) create a table of 256
elements in length. -which I have verified to function in a circuit
BTW-  However, I have noticed that there are certain sequences of
values (most, in fact) that will give me errors: "too many Product
terms" for each bit of the 4 bit output. So my approach is apparently
not the "general solution" that I need. (I have the data for the parts
that I need to emulate, and they appear to be "random" values) There
does not appear to be any optimization selection that helps either.

I have also tried using the AT750x series, hoping that the additional
gates would help. -Same issue.

Atmel technical support tried to help, however, I was unable to
communicate my problem well enough. I was provided a modified example
of "Lookup.pld". The issue I have with the example they sent is that
there are still only 6 bits of input used, and even though I tried my
best to expand the provided solution, I almost always (eventually)
ended up with the same issue -not enough product terms.

I am wondering if its possible to use some of the address bits (lets
say 2 for example), that would be used to "select" which table to use.
IOW, the 2 bits would select one of 4 tables, each of six bits in
length to address the proper element in the table. Would doing this
save product terms?

I cannot get the above approach to work either. This was the approach
I pitched to Atmel tech support, and was told that it should work,
although like I said earlier, the example provided, was not
sufficient. perhaps I am missing something(???)

What bothers me the most about the issue is that I am trying to re-
create something that was created back in the late '70s to early '80s,
the chips obviously function, so I am wondering how it was done. I am
using a 21st century development tool with optimizers, etc....

I was up until 2:30 last night struggling with this. (and I'm not
counting the countless hours already spent over the past few weeks)

Please Help if you have any ideas!. I do not want to resort to using
High-density CPLDs or FPGAs (size & cost are the main isssues with
that)

Sorry if this email was long-winded, but I wanted to explain my
problem with enough fidelity to hopefully get some real help. Thank
you for reading all of this!

On Oct 24, 12:20=A0pm, eubankss...@gmail.com wrote:
> I am fairly new to CPL development, and I need to create an emulation
> of a number of old bipolar Proms (256x4) being used in a very old
> system by using a CPLD and WInCUPL.
>
> My approach was to use the example "Lookup.pld" as a basis for my LUT,
> with the exception that I am trying to use 8 bits of address to
> produce a 4 bit output for each of the possible 256 inputs.
>
> Using an AT22V10, I am able to (sometimes) create a table of 256
> elements in length. -which I have verified to function in a circuit
> BTW- =A0However, I have noticed that there are certain sequences of
> values (most, in fact) that will give me errors: "too many Product
> terms" for each bit of the 4 bit output. So my approach is apparently
> not the "general solution" that I need. (I have the data for the parts
> that I need to emulate, and they appear to be "random" values) There
> does not appear to be any optimization selection that helps either.
>
> I have also tried using the AT750x series, hoping that the additional
> gates would help. -Same issue.
>
> Atmel technical support tried to help, however, I was unable to
> communicate my problem well enough. I was provided a modified example
> of "Lookup.pld". The issue I have with the example they sent is that
> there are still only 6 bits of input used, and even though I tried my
> best to expand the provided solution, I almost always (eventually)
> ended up with the same issue -not enough product terms.
>
> I am wondering if its possible to use some of the address bits (lets
> say 2 for example), that would be used to "select" which table to use.
> IOW, the 2 bits would select one of 4 tables, each of six bits in
> length to address the proper element in the table. Would doing this
> save product terms?
>
> I cannot get the above approach to work either. This was the approach
> I pitched to Atmel tech support, and was told that it should work,
> although like I said earlier, the example provided, was not
> sufficient. perhaps I am missing something(???)
>
> What bothers me the most about the issue is that I am trying to re-
> create something that was created back in the late '70s to early '80s,
> the chips obviously function, so I am wondering how it was done. I am
> using a 21st century development tool with optimizers, etc....
>
> I was up until 2:30 last night struggling with this. (and I'm not
> counting the countless hours already spent over the past few weeks)
>
> Please Help if you have any ideas!. I do not want to resort to using
> High-density CPLDs or FPGAs (size & cost are the main isssues with
> that)
>
> Sorry if this email was long-winded, but I wanted to explain my
> problem with enough fidelity to hopefully get some real help. Thank
> you for reading all of this!

If you can live with more than one macrocell delay you may be able to
get more tables to work.  Using just the 8 ins and 4 outs will always
be limited by the product terms and rule out certain tables even if
they have very simple structure like the exclusive OR of all the
inputs.  Using more than one level of logic (with a 22V10 you
can have 6 macrocells feeding back into your design in addition
to the 4 outputs) you may be able to get your job done, but
it will cost you in the output delay time.  I had similar issues
making a parallel 8b10b encoder and decoder, but found that
with mach210 I could use two levels of logic and do it quite
handily.

The other obvious approach is to actually use a PROM if
you can find one within your budget (speed, size and $$).
I had used small synchronous PROMs from Cypress in
my original 8b10b design, but back then they were more
expensive than a CPLD.

Regards,
Gabor

On Oct 24, 9:20 am, eubankss...@gmail.com wrote:
>
> What bothers me the most about the issue is that I am trying to re-
> create something that was created back in the late '70s to early '80s,
> the chips obviously function, so I am wondering how it was done. I am
> using a 21st century development tool with optimizers, etc....
>

It's not a 'this century' vs/ 'last century' issue.  It's a device
capability issue.

Decoding in the PROM you mention is like having 256 OR terms for every
output.

You PAL has (IIRC) 12 OR terms max per output.

And 256 is larger than 12.  True last century, true this.  ;)

eubanksster@gmail.com wrote:

> I am fairly new to CPL development, and I need to create an emulation
> of a number of old bipolar Proms (256x4) being used in a very old
> system by using a CPLD and WInCUPL.
> 
> My approach was to use the example "Lookup.pld" as a basis for my LUT,
> with the exception that I am trying to use 8 bits of address to
> produce a 4 bit output for each of the possible 256 inputs.
> 
> Using an AT22V10, I am able to (sometimes) create a table of 256
> elements in length. -which I have verified to function in a circuit
> BTW-  However, I have noticed that there are certain sequences of
> values (most, in fact) that will give me errors: "too many Product
> terms" for each bit of the 4 bit output. So my approach is apparently
> not the "general solution" that I need. (I have the data for the parts
> that I need to emulate, and they appear to be "random" values) There
> does not appear to be any optimization selection that helps either.
> 
> I have also tried using the AT750x series, hoping that the additional
> gates would help. -Same issue.
> 
> Atmel technical support tried to help, however, I was unable to
> communicate my problem well enough. I was provided a modified example
> of "Lookup.pld". The issue I have with the example they sent is that
> there are still only 6 bits of input used, and even though I tried my
> best to expand the provided solution, I almost always (eventually)
> ended up with the same issue -not enough product terms.
> 
> I am wondering if its possible to use some of the address bits (lets
> say 2 for example), that would be used to "select" which table to use.
> IOW, the 2 bits would select one of 4 tables, each of six bits in
> length to address the proper element in the table. Would doing this
> save product terms?
> 
> I cannot get the above approach to work either. This was the approach
> I pitched to Atmel tech support, and was told that it should work,
> although like I said earlier, the example provided, was not
> sufficient. perhaps I am missing something(???)
> 
> What bothers me the most about the issue is that I am trying to re-
> create something that was created back in the late '70s to early '80s,
> the chips obviously function, so I am wondering how it was done. I am
> using a 21st century development tool with optimizers, etc....
> 
> I was up until 2:30 last night struggling with this. (and I'm not
> counting the countless hours already spent over the past few weeks)
> 
> Please Help if you have any ideas!. I do not want to resort to using
> High-density CPLDs or FPGAs (size & cost are the main isssues with
> that)
> 
> Sorry if this email was long-winded, but I wanted to explain my
> problem with enough fidelity to hopefully get some real help. Thank
> you for reading all of this!
> 
> 
If you look in detail, I think you can see the difficulty in what
you are doing.  Look at one bit. You want that bit to be high at
a certain number of 8 bit addresses.  To decode this, you need to
decode each of those addresses (subject to some small amount of
optimization but ignore that for a minute) and then OR the results
together.  If a bit is high for 100 addresses, you need to have
100 8 bit decoders and a 100 bit OR gate.  That is very expensive
in terms of logic resources.

If you want a memory, it is better to use a memory.

> 
> 

Thank you for offering this solution. I would like to experiment with
this approach. But I am not sure if I understand what the CUPL code
would look like to do this.

Are you saying that instead of 4 bit outputs (what I have now) that I
would instead use some bits of the outputs going back into the chip?
For example, if I used 6 bits of output, are you saying that I would
use the additional 2 bits to somehow perform a 1-of-4 selector that
would select a given table of each table having a length of -in this
example- 64 addresses?

If I could see a short code snippet, I think it would help me to
understand this better.




> If you can live with more than one macrocell delay you may be able to
> get more tables to work. =A0Using just the 8 ins and 4 outs will always
> be limited by the product terms and rule out certain tables even if
> they have very simple structure like the exclusive OR of all the
> inputs. =A0Using more than one level of logic (with a 22V10 you
> can have 6 macrocells feeding back into your design in addition
> to the 4 outputs) you may be able to get your job done, but
> it will cost you in the output delay time. =A0I had similar issues
> making a parallel 8b10b encoder and decoder, but found that
> with mach210 I could use two levels of logic and do it quite
> handily.

I have tried to locate a "real" datasheet for the PROM's (MB7052) but
have only found pinouts, no detailed description of how they were
used. Were MB7052s also programmed using a compiled form of Boolean
expressions just like the part(s) I am using?

Since you describe them as having 256 OR terms, then I am thinking
that the architecture of these older devices is somewhat similar to
the one I am using. Due to the small size (16 pin DIP) then I am
curious if perhaps there is an alternate solution by using a different
(modern) part. It seems that from a functional point-of-view, I need a
256-by-4 memory chip. (these days its easy to find 256 *MegaBytes*!
but 256-by-4 sounds like a joke by today's standards ;>) My form-
factor requirements preclude the use of most of the high-density CPLDs
(I think)

Is there by chance a vendor that that you know of that currently
provides CPLDs that would meet my capacity requirements but packaged
as a small SOIC or similar? (IOW, something that could easily fit
within the size of a 16 pin DIP)  I have looked around, but most go
down to 44pin QFP which would still be too large.

thanks again for your input.


On Oct 24, 5:01=A0pm, d_s_kl...@yahoo.com wrote:
> On Oct 24, 9:20 am, eubankss...@gmail.com wrote:
>
>
>
> > What bothers me the most about the issue is that I am trying to re-
> > create something that was created back in the late '70s to early '80s,
> > the chips obviously function, so I am wondering how it was done. I am



> > using a 21st century development tool with optimizers, etc....
>
> It's not a 'this century' vs/ 'last century' issue. =A0It's a device
> capability issue.
>
> Decoding in the PROM you mention is like having 256 OR terms for every
> output.
>
> You PAL has (IIRC) 12 OR terms max per output.
>
> And 256 is larger than 12. =A0True last century, true this. =A0;)

eubanksster@gmail.com wrote:

> I have tried to locate a "real" datasheet for the PROM's (MB7052) but
> have only found pinouts, no detailed description of how they were
> used. Were MB7052s also programmed using a compiled form of Boolean
> expressions just like the part(s) I am using?

These are memory chips, they are not CPLDs. Each address is
programmed with the data they wanted.
> 
> Since you describe them as having 256 OR terms, then I am thinking
> that the architecture of these older devices is somewhat similar to
> the one I am using. 

No, they do not have the same architecture at all.  The memory chip
has 1024 memory locations set up as 256x4, each group of four is
addressed by an 8 bit AND to pick the address. There is effectively a
256 to 1 multiplexer to select which of the memory elements is
sent to the output pins. Often this was a wired OR for simplicity.

The CPLD is intended as a logic device.  Since you do not have
1024 memory storage units in the CPLD, you have to make it up
with logic.  Suppose bit 1 is high at address 1 and 10.  You have
to decode adresses 1 with an 8 bit AND and you have to decode
address 10 with another 8 bit AND.  You then need a 2 bit OR to
allow both addresses.

In general, a memory would be done as something like
bit1 = addra or addrb or addrc or addrd ...

Where addra, addrb etc are the addresses that you want to have the
bit =1. Each of the addra etc are 8 bit ANDs (assuming that each of
the inputs has a polarity invert. If not, then you need 16 line
available).  If an output bit is high for half of the addresses,
you have used up 128 8 bit ANDs. Times 4 that is a lot of
logic.  Your CPLD has maybe 10 of these.  They are not meant to be
memories.

Due to the small size (16 pin DIP) then I am
> curious if perhaps there is an alternate solution by using a different
> (modern) part. It seems that from a functional point-of-view, I need a
> 256-by-4 memory chip. (these days its easy to find 256 *MegaBytes*!
> but 256-by-4 sounds like a joke by today's standards ;>) My form-
> factor requirements preclude the use of most of the high-density CPLDs
> (I think)

If you need a memory, use a memory. Get a large memory and only use
part of it.  You can get flash memory in a variety of small
packages and even though you will have megabytes of memory, you
only need to use what you want.
> 
> Is there by chance a vendor that that you know of that currently
> provides CPLDs that would meet my capacity requirements but packaged
> as a small SOIC or similar? (IOW, something that could easily fit
> within the size of a 16 pin DIP)  I have looked around, but most go
> down to 44pin QFP which would still be too large.

You want a memory chip, not a CPLD.
> 
> thanks again for your input.
> 
> 
> On Oct 24, 5:01 pm, d_s_kl...@yahoo.com wrote:
> 
>>On Oct 24, 9:20 am, eubankss...@gmail.com wrote:
>>
>>
>>
>>
>>>What bothers me the most about the issue is that I am trying to re-
>>>create something that was created back in the late '70s to early '80s,
>>>the chips obviously function, so I am wondering how it was done. I am
> 
> 
> 
> 
>>>using a 21st century development tool with optimizers, etc....
>>
>>It's not a 'this century' vs/ 'last century' issue.  It's a device
>>capability issue.
>>
>>Decoding in the PROM you mention is like having 256 OR terms for every
>>output.
>>
>>You PAL has (IIRC) 12 OR terms max per output.
>>
>>And 256 is larger than 12.  True last century, true this.  ;)
> 
> 

hmmm... I've replied to some of the posts here (thanks for your
input)  but my new posts do not show up! I am not sure if my replies
have actually been sent!.

eubanksster@gmail.com wrote:
> I am fairly new to CPL development, and I need to create an emulation
> of a number of old bipolar Proms (256x4) being used in a very old
> system by using a CPLD and WInCUPL.

What are the PROMS doing ?


> My approach was to use the example "Lookup.pld" as a basis for my LUT,
> with the exception that I am trying to use 8 bits of address to
> produce a 4 bit output for each of the possible 256 inputs.
> 
> Using an AT22V10, I am able to (sometimes) create a table of 256
> elements in length. -which I have verified to function in a circuit
> BTW-  However, I have noticed that there are certain sequences of
> values (most, in fact) that will give me errors: "too many Product
> terms" for each bit of the 4 bit output. So my approach is apparently
> not the "general solution" that I need. (I have the data for the parts
> that I need to emulate, and they appear to be "random" values) There
> does not appear to be any optimization selection that helps either.
<snip>

If you consider no logic optimisation, you will need 256 Product terms.
The good news is, CUPL will optimise (and has -M2/M3/M4 switches to do
so, and it CAN reduce the PTs needed - but (more bad news:) only so far.

You CAN pack a 7 segment decoder, to around 20 charatcers into 8 PT, or
a Decimal-7 segment into 2-3-4 product terms, so a typical 'packing 
ratio' of up to 3:1 is indicated.
That drops your 256 to the region of 80!

So any solution is VERY prom content dependant.
You have to hope those proms, are 'coarse' in what they do, if they are
granular, and more random, you are sweet out of luck.

What does CUPL actually report as the PT usage, with  highest optimise 
setting, for each BIT of your PROMS ?
That should be in the report files.

Knowing what the proms are actually DOING, would help here.
It is unlikely they are _really_ random

You CAN trade off some outputs as INTERMEDIATE product terms, and so
cascade PTs, but a 22V10 must average under ~34.5PT/4 bits, to fit
(working from memory).
Doing that cascade is not something the tools automate, but CUPL
WILL swallow intermediate terms not PIN defined, so you can code the 
PROM into blocks, and see how the block compress.


<paste>
> Is there by chance a vendor that that you know of that currently
> provides CPLDs that would meet my capacity requirements but packaged
> as a small SOIC or similar? (IOW, something that could easily fit
> within the size of a 16 pin DIP)  I have looked around, but most go
> down to 44pin QFP which would still be too large.

PLCC32 is not far off ? - that would allow a 27E512, which is a curent
device and will exactly emulate your PROM. (unless the last ns matters)

-jg

On Oct 27, 4:10=A0am, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> eubankss...@gmail.com wrote:
> > I am fairly new to CPL development, and I need to create an emulation
> > of a number of old bipolar Proms (256x4) being used in a very old
> > system by using a CPLD and WInCUPL.
>
[snip]

> > Is there by chance a vendor that that you know of that currently
> > provides CPLDs that would meet my capacity requirements but packaged
> > as a small SOIC or similar? (IOW, something that could easily fit
> > within the size of a 16 pin DIP) =A0I have looked around, but most go
> > down to 44pin QFP which would still be too large.
>
> PLCC32 is not far off ? - that would allow a 27E512, which is a curent
> device and will exactly emulate your PROM. (unless the last ns matters)
>
> -jg

Cypress makes NV RAMs in very small packages.  The 1M parts
come in SSOP.  25nS access time and "hands off" power down storage.
If you don't need to change the content on the fly you could just
program them once and tie the write enable off...