Re: Register File distributed all over the FPGA

On 2008-10-28, Philipp <Patrick.Bateman23@gmx.at> wrote:
> Hi
>
> I have implemented a very simple processor architecture and I was now 
> taking a closer look at the floorplan using the Xilinx toolset. What I 
> saw there is rather strange. It not only seems that all the Registers of 
> the register file are
> distributed all over the FPGA, even the single bits of the registers are 
> located at completly different locations. So I wonder if there is a 
> chance to tell ISE that it should instantiate a logic block that holds 
> all the registers of the register file in logic cells located next to 
> each other?

There is a constraint called RLOC_RANGE which you might want to look into.
It could probably help you with this.

However, I would recommend that you look at your timing report to see if
you would actually benefit from trying to optimize the register file at
this point. If your critical path is not located in the register file you
don't gain much by optimizing the register file...

/Andreas

On 2008-10-28, Philipp <Patrick.Bateman23@gmx.at> wrote:
> Its not about optimizing for speed or area. But for my purposes (we 
> wanna measure the EM of the register file) it would be helpful if the
> registers are grouped all together!

I see. This sounds pretty interesting, perhaps you could post something to
this newsgroup once you have some results?

In what context are you trying to measure this? Security research?

/Andreas

Hi

I have implemented a very simple processor architecture and I was now 
taking a closer look at the floorplan using the Xilinx toolset. What I 
saw there is rather strange. It not only seems that all the Registers of 
the register file are
distributed all over the FPGA, even the single bits of the registers are 
located at completly different locations. So I wonder if there is a 
chance to tell ISE that it should instantiate a logic block that holds 
all the registers of the register file in logic cells located next to 
each other?

Many thanks,
Philipp

> There is a constraint called RLOC_RANGE which you might want to look into.
> It could probably help you with this.

Thanks, I will take a look into this!

> However, I would recommend that you look at your timing report to see if
> you would actually benefit from trying to optimize the register file at
> this point. If your critical path is not located in the register file you
> don't gain much by optimizing the register file...

Its not about optimizing for speed or area. But for my purposes (we 
wanna measure the EM of the register file) it would be helpful if the
registers are grouped all together!

> Its not about optimizing for speed or area. But for my purposes (we  
> wanna measure the EM of the register file) it would be helpful if the
> registers are grouped all together!

In this case you need to look into Synthesis Constraints such as RLOC (as  
was advised before) or AREA_GROUP.
The latter worked for me better - as you can manually forse the design to  
be located where you want (exact slice coordinates).


-- 
Alex

> I see. This sounds pretty interesting, perhaps you could post something to
> this newsgroup once you have some results?
> 
> In what context are you trying to measure this? Security research?

Yes, exactly. Will keep you up to date as soon as we have obtained some 
results!

Cheerios,
Philipp

> In this case you need to look into Synthesis Constraints such as RLOC 
> (as was advised before) or AREA_GROUP.
> The latter worked for me better - as you can manually forse the design 
> to be located where you want (exact slice coordinates).

Cheers Alex, will have a look at the AREA_GROUP Contrainst. The only 
problem is, that my register file is not instantiated in the top level 
of the design and this seems to be a precondition.

Cheers,
Philipp

>> In this case you need to look into Synthesis Constraints such as RLOC  
>> (as was advised before) or AREA_GROUP.
>> The latter worked for me better - as you can manually forse the design  
>> to be located where you want (exact slice coordinates).
>
> Cheers Alex, will have a look at the AREA_GROUP Contrainst. The only  
> problem is, that my register file is not instantiated in the top level  
> of the design and this seems to be a precondition.
>
> Cheers,
> Philipp

Don't see any problem with that, as long as you know your hierarchy and  
the name of the
instance you want to constrain. For example

AREA_GROUP "AG_reg_file" RANGE =  
SLICE_X24Y12:SLICE_X25Y12,SLICE_X23Y13:SLICE_X26Y13
INST "top/h1/h2/YOUR_REG_FILE" AREA_GROUP = "AG_reg_file"


-- 
Alex

On 2008-10-29, Philipp <Patrick.Bateman23@gmx.at> wrote:
> Alex wrote:
>> First make sure that keep hierarchy is on (you might want to try to 
>> place directly to the UCF file).
>> Also check that your register file is still there after synthesis, i.e. 
>> it has not been optimized or combined with
>> something else (in case of memory - it could well be the case).
>> To chek it  - try
>> INST "Testbench/ARC_Ndp/Arc_Reg_File" OPTIMIZE=OFF;
>> and see if this helps.
>
>
> Cheers Alex, I have to leave now but will try it tomorrow and let you 
> know if it helped!

Another reason that this doesn't work might be that the hierarchy separator
is set to _ instead of /. Take a look in the floorplanner to see what the
name of the unit really is if you haven't done so already.

/Andreas

> Don't see any problem with that, as long as you know your hierarchy and 
> the name of the
> instance you want to constrain. For example
> 
> AREA_GROUP "AG_reg_file" RANGE = 
> SLICE_X24Y12:SLICE_X25Y12,SLICE_X23Y13:SLICE_X26Y13
> INST "top/h1/h2/YOUR_REG_FILE" AREA_GROUP = "AG_reg_file"

Cheers Alex, I tried as you suggested but there seems to be a problem...

INST "Testbench/ARC_Ndp/Arc_Reg_File" AREA_GROUP = g1;
AREA_GROUP "g1" RANGE = SLICE_X10Y10,SLICE_X100Y100;

But then I get the following error message:

ERROR:ConstraintSystem:59 - Constraint <INST 
"Testbench/ARC_Ndp/Arc_Reg_File"
    AREA_GROUP = g1;> [ndp.ucf(6)]: INST 
"Testbench/ARC_Ndp/Arc_Reg_File" 	not found.  Please verify that:
    1. The specified design element actually exists in the originadesign.
    2. The specified object is spelled correctly in the constraint 
source file.

I am quite sure that this is the hiercharchical path to my Reg_file as I 
instantiate in the topmodule Testbench the unit ARC_Ndp (derived from 
NdpWidth.vhd) and then in ARC_Ndp in instatiate ARC_Reg_File (derived 
from Reg_file.vhd). Is it maybe really possible that the unit I wanna 
group has to be in the top module?

Thanks,
Philipp