ISE 9.2.03i problem

Hi Xilinx gurus,


I've got some code which I've been running on Altera silcon for several
weeks now, used in a number of different projects, synthesized with
Quartus v8.

It's a simple shift register implemented using a variable in a clocked
process...

process (reset, clk, clk_ena)
  variable hactive_v_r  : std_logic_vector(3 downto 0) := (others => '0');
begin
  if reset = '1' then
    hactive_v_r := (others => '0');
  elsif rising_edge(clk) and clk_ena = '1' then
    ...
    hactive_v_r := hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s;
  end if;
end process;

BTW 'h_active_s' is a signal declared in the containing entity, and is
definitely not optimised out.

However, when building the project for Xilix under ISE 9.2.03i, I get the
following warnings during synthesis:

WARNING:Xst:653 - Signal <hactive_v_r<3>> is used but never assigned. Tied
to value 0.
WARNING:Xst:1780 - Signal <hactive_v_r<2:0>> is never used or assigned.

As a result, the code doesn't work - the results suggest that this shift
register has indeed been removed from the design.

As I said, this module is used - exactly as-is, in its entirety, in
several Altera modules.

Any idea what my problem is???

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:

Interesting - if I change the variables to signals, it works!

Bug?

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

On Oct 29, 10:45=A0am, Mark McDougall <ma...@vl.com.au> wrote:
> Mark McDougall wrote:
>
> Interesting - if I change the variables to signals, it works!
>
> Bug?
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266

My understanding from VHDL point of view is that VARIABLES are visible
only inside process and since not assigned to signal it is optimised.
Is variable "hactive_v_r" being read some where else in code and are
you able to compile it? You should get compilation
error.
Sandeep

On Oct 29, 10:45=A0am, Mark McDougall <ma...@vl.com.au> wrote:
> Mark McDougall wrote:
>
> Interesting - if I change the variables to signals, it works!
>
> Bug?
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266

My understanding is that VARIABLES are visible only inside the process
and hence getting optimised. Is the variable
"hactive_v_r" read/used in other part of code and are you able to
compile the code? You should get compilation error too.
--Sandeep

On Wed, 29 Oct 2008 13:24:46 +1100, Mark McDougall <markm@vl.com.au>
wrote:

>Hi Xilinx gurus,
>
>
>I've got some code which I've been running on Altera silcon for several
>weeks now, used in a number of different projects, synthesized with
>Quartus v8.
>
>It's a simple shift register implemented using a variable in a clocked
>process...
>
>process (reset, clk, clk_ena)
>  variable hactive_v_r  : std_logic_vector(3 downto 0) := (others => '0');
>begin
>  if reset = '1' then
>    hactive_v_r := (others => '0');
>  elsif rising_edge(clk) and clk_ena = '1' then
>    ...
>    hactive_v_r := hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s;
>  end if;
>end process;

>As I said, this module is used - exactly as-is, in its entirety, in
>several Altera modules.
>
>Any idea what my problem is???

As written here, XST appears to be correct. 

hactive_v_r is a variable, assigned as the last line of the process, and
not used anywhere in the process (except in assignment to itself). As a
variable local to the process, it has no visibility outside the process,
so XST may optimise it out.

There is something else going on, that you haven't shown us.

- Brian

Brian Drummond wrote:

> There is something else going on, that you haven't shown us.

Yeah, sorry, it is used elsewhere in the process in an 'if' statement, to
assign the value of a signal.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

I've little experience with ISE & its idiosyncrasies, but I've since been
told that this type of problem isn't uncommon. Apparently it's a little
too aggressive with its optimisation where duplicate logic is removed...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:
> I've little experience with ISE & its idiosyncrasies, but I've since been
> told that this type of problem isn't uncommon. Apparently it's a little
> too aggressive with its optimisation where duplicate logic is removed...

Not sure who told you that, but I do that sort of thing all the time 
with variables in ISE 9.2, and have never had a bit of trouble. If you 
want to see a program that is extremely aggressive about finding and 
removing duplicate logic, try out Synplify sometime. But removing 
duplicate logic is a good thing, not bad.

About the only difference in the way I code things is that I always put 
the clock enable within the clocked part of the process, and never in 
the sensitivity list (a clock enable should not be put there anyway).

> process (reset, clk, clk_ena)
> =A0 variable hactive_v_r =A0: std_logic_vector(3 downto 0) :=3D (others =
=3D> '0');
> begin
> =A0 if reset =3D '1' then
> =A0 =A0 hactive_v_r :=3D (others =3D> '0');
> =A0 elsif rising_edge(clk) and clk_ena =3D '1' then
> =A0 =A0 ...
> =A0 =A0 hactive_v_r :=3D hactive_v_r(hactive_v_r'left-1 downto 0) & hacti=
ve_s;
> =A0 end if;
> end process;
>
> BTW 'h_active_s' is a signal declared in the containing entity, and is
> definitely not optimised out.
>
> However, when building the project for Xilix under ISE 9.2.03i, I get the
> following warnings during synthesis:
>
> WARNING:Xst:653 - Signal <hactive_v_r<3>> is used but never assigned. Tie=
d
> to value 0.
> WARNING:Xst:1780 - Signal <hactive_v_r<2:0>> is never used or assigned.
>

Could it be that you have a signal declared which has the same name as
the variable? Does anyone know if XST still warns that a signal is
being removed, even if it's actually a variable?

If there were a signal by the same name which is being optimized away,
maybe XST gets confused and gets rid of both.

Dave

On Oct 29, 7:35=A0pm, Mark McDougall <ma...@vl.com.au> wrote:
> I've little experience with ISE & its idiosyncrasies, but I've since been
> told that this type of problem isn't uncommon. Apparently it's a little
> too aggressive with its optimisation where duplicate logic is removed...
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266

I would also expect this to create flops, exactly as you seem to want.
Without the full details of the rest of your code, I took an educated
guess and made up some logic (foo). I tried out the following design
in ISE 9.1.02i and it created some nontrivial logic for hactive_v_r(3
downto 0), after synthesis (only, into the default xcv5vlx50 device)
and a glance at the RTL viewer.

Two other tangential thoughts crossed my mind as well:

(1) why do you have clk_ena in the sensitivity list? Here in the
Castle Anthrax there's only one punishment for random, desparate-
looking sensitivity lists :-)

(2) the question has often arisen here, as to why std_logic_arith and
std_logic_unsigned keep rearing their ugly heads in otherwise well-
intentioned code. One answer appeared when I (despite my better
instincts, and due to sheer laziness) used that damn-fool Xilinx
design entry wizard to create the top level shown below.  "If Xilinx
does it, it must be right!", right?

Cheers, new Bruce.

 - Kenn

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fidget is
    Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           clk_ena : in  STD_LOGIC;
           hactive_input : in  STD_LOGIC;
           foo_output : out  STD_LOGIC);
end fidget;

architecture Behavioral of fidget is
  signal foo : std_logic;
  signal hactive_s : std_logic;
begin
  hactive_s <=3D hactive_input;
  foo_output <=3D foo;

  process (reset, clk, clk_ena)
    variable hactive_v_r  : std_logic_vector(3 downto 0) :=3D (others =3D>
'0');
  begin
    if reset =3D '1' then
      hactive_v_r :=3D (others =3D> '0');
    elsif rising_edge(clk) and clk_ena =3D '1' then
	   if hactive_v_r =3D "0000" then
		    foo <=3D not foo;
		end if;

      hactive_v_r :=3D hactive_v_r(hactive_v_r'left-1 downto 0) &
hactive_s;
    end if;
  end process;

end Behavioral;