How to move project files from ISE 7.1 to ISE 10.1

Hello Guys,

I am trying to move a current project files that contain PCI Xilinx IP
Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
project. The ISE 7.x does not have "export source" function. Also, I
have tried to move the following files: (.v , .xco and .ucf) and have
created a new project with the same target and same name in ISE 10.1
and started adding the source files (.v , .xco and .ucf). That allowed
me to synthesize the project successully but did not allow me to
implement the design. It fails from the first step "translate" ! and
lists the following log:


Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <NET "PCI_CORE/AD_IO<0>"  LOC =
"T8" |>
   [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found.  Please
verify that:
   1. The specified design element actually exists in the original
design.
   2. The specified object is spelled correctly in the constraint
source file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 |>
   [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found.  Please
verify that:
   1. The specified design element actually exists in the original
design.
   2. The specified object is spelled correctly in the constraint
source file.

ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |>
[SigC6415.ucf(68)]: NET
   "PCI_CORE/AD_IO<0>" not found.  Please verify that:
   1. The specified design element actually exists in the original
design.
   2. The specified object is spelled correctly in the constraint
source file.

..... and alot of similar error messages (ERROR:ConstraintSystem:59 )

I have tried also to do "clean up project" but that did not solve the
p[roblem. So what could be the thing that I am missing?

On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote:
> Hello Guys,
>
> I am trying to move a current project files that contain PCI Xilinx IP
> Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
> project. The ISE 7.x does not have "export source" function. Also, I
> have tried to move the following files: (.v , .xco and .ucf) and have
> created a new project with the same target and same name in ISE 10.1
> and started adding the source files (.v , .xco and .ucf). That allowed
> me to synthesize the project successully but did not allow me to
> implement the design. It fails from the first step "translate" ! and
> lists the following log:
>

Why are you making it so hard?  Just make a copy of the -entire-
ISE-7.1 project (sub-directories and all) and open the project with
ISE-10.1

ISE will convert is for you.

Alex

On Nov 3, 5:11=A0pm, LittleAlex <alex.lo...@email.com> wrote:
> On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote:
>
> > Hello Guys,
>
> > I am trying to move a current project files that contain PCI Xilinx IP
> > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
> > project. The ISE 7.x does not have "export source" function. Also, I
> > have tried to move the following files: (.v , .xco and .ucf) and have
> > created a new project with the same target and same name in ISE 10.1
> > and started adding the source files (.v , .xco and .ucf). That allowed
> > me to synthesize the project successully but did not allow me to
> > implement the design. It fails from the first step "translate" ! and
> > lists the following log:
>
> Why are you making it so hard? =A0Just make a copy of the -entire-
> ISE-7.1 project (sub-directories and all) and open the project with
> ISE-10.1
>
> ISE will convert is for you.
>
> Alex

Hello Alex,

Thanks for your reply... I have tried that also and ISE asked me to
convert it and make automatically a backupfile of the old one
but ..... unfortunately I end up with the same errors... I have to
emphasis that there is an IP core used in the project. so maybe I have
to set up the ISE 10.1 to recognize the IPcores available in the other
station were ISE7.1 resides. So probably there is a procedure I need
to follow or so? Any clues :(

On Nov 4, 6:48=A0am, y.tachw...@gmail.com wrote:
> On Nov 3, 5:11=A0pm, LittleAlex <alex.lo...@email.com> wrote:
>
>
>
>
>
> > On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote:
>
> > > Hello Guys,
>
> > > I am trying to move a current project files that contain PCI Xilinx I=
P
> > > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
> > > project. The ISE 7.x does not have "export source" function. Also, I
> > > have tried to move the following files: (.v , .xco and .ucf) and have
> > > created a new project with the same target and same name in ISE 10.1
> > > and started adding the source files (.v , .xco and .ucf). That allowe=
d
> > > me to synthesize the project successully but did not allow me to
> > > implement the design. It fails from the first step "translate" ! and
> > > lists the following log:
>
> > Why are you making it so hard? =A0Just make a copy of the -entire-
> > ISE-7.1 project (sub-directories and all) and open the project with
> > ISE-10.1
>
> > ISE will convert is for you.
>
> > Alex
>
> Hello Alex,
>
> Thanks for your reply... I have tried that also and ISE asked me to
> convert it and make automatically a backupfile of the old one
> but ..... unfortunately I end up with the same errors... I have to
> emphasis that there is an IP core used in the project. so maybe I have
> to set up the ISE 10.1 to recognize the IPcores available in the other
> station were ISE7.1 resides. So probably there is a procedure I need
> to follow or so? Any clues :(- Hide quoted text -
>
> - Show quoted text -



Did you try option "Regenerate all cores" before performing synthesis.
I one of my experiences, I was unable to synthesize an ISE-7.1 design
in ISE-8.2 till I regenerated all cores.

Hope this Helps

Regards
/MH

On Mon, 3 Nov 2008 15:58:13 -0800 (PST), y.tachwali@gmail.com wrote:

>Hello Guys,
>
>I am trying to move a current project files that contain PCI Xilinx IP
>Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
>project. 

It sounds liek the process you have followed is reasonable...

perhaps it's worth focussing on the actual error?

>ERROR:ConstraintSystem:59 - Constraint <NET "PCI_CORE/AD_IO<0>"  LOC =
>"T8" |>
>   [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found.  
>..... and alot of similar error messages (ERROR:ConstraintSystem:59 )

I would suggest generating a post-synthesis simulation netlist, opening
it in a text editor, and searching for "AD_IO". (I find this easier to
use than the RTL view for this sort of purpose!)

You may find nets called
"PCI_CORE_AD_IO<0>" (where the hierarchy separator is "_" not"/")
or
"MY_MODULE/PCI_CORE/AD_IO<0>" (where the hierarchical name has been
extended) or simply "ADIO<0>" where it has been shortened, 
or some similar change.

The first can be fixed by setting the hierarchy separator character (on
the "Synthesis Properties" dialog); others may be fixable by editing the
relevant UCF constraints to reflect the actual signal names.

- Brian

On Nov 4, 1:59=A0am, Moazzam <moazzamhuss...@gmail.com> wrote:
> On Nov 4, 6:48=A0am, y.tachw...@gmail.com wrote:
>
>
>
>
>
> > On Nov 3, 5:11=A0pm, LittleAlex <alex.lo...@email.com> wrote:
>
> > > On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote:
>
> > > > Hello Guys,
>
> > > > I am trying to move a current project files that contain PCI Xilinx=
 IP
> > > > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
> > > > project. The ISE 7.x does not have "export source" function. Also, =
I
> > > > have tried to move the following files: (.v , .xco and .ucf) and ha=
ve
> > > > created a new project with the same target and same name in ISE 10.=
1
> > > > and started adding the source files (.v , .xco and .ucf). That allo=
wed
> > > > me to synthesize the project successully but did not allow me to
> > > > implement the design. It fails from the first step "translate" ! an=
d
> > > > lists the following log:
>
> > > Why are you making it so hard? =A0Just make a copy of the -entire-
> > > ISE-7.1 project (sub-directories and all) and open the project with
> > > ISE-10.1
>
> > > ISE will convert is for you.
>
> > > Alex
>
> > Hello Alex,
>
> > Thanks for your reply... I have tried that also and ISE asked me to
> > convert it and make automatically a backupfile of the old one
> > but ..... unfortunately I end up with the same errors... I have to
> > emphasis that there is an IP core used in the project. so maybe I have
> > to set up the ISE 10.1 to recognize the IPcores available in the other
> > station were ISE7.1 resides. So probably there is a procedure I need
> > to follow or so? Any clues :(- Hide quoted text -
>
> > - Show quoted text -
>
> Did you try option "Regenerate all cores" before performing synthesis.
> I one of my experiences, I was unable to synthesize an ISE-7.1 design
> in ISE-8.2 till I regenerated all cores.
>
> Hope this Helps
>
> Regards
> /MH- Hide quoted text -
>
> - Show quoted text -

Thank you for your reply... this attempt did not work... I am still
having the same errors :(

On Nov 4, 4:53=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 3 Nov 2008 15:58:13 -0800 (PST), y.tachw...@gmail.com wrote:
> >Hello Guys,
>
> >I am trying to move a current project files that contain PCI Xilinx IP
> >Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the
> >project.
>
> It sounds liek the process you have followed is reasonable...
>
> perhaps it's worth focussing on the actual error?
>
> >ERROR:ConstraintSystem:59 - Constraint <NET "PCI_CORE/AD_IO<0>" =A0LOC =
=3D
> >"T8" |>
> > =A0 [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found. =A0
> >..... and alot of similar error messages (ERROR:ConstraintSystem:59 )
>
> I would suggest generating a post-synthesis simulation netlist, opening
> it in a text editor, and searching for "AD_IO". (I find this easier to
> use than the RTL view for this sort of purpose!)
>
> You may find nets called
> "PCI_CORE_AD_IO<0>" (where the hierarchy separator is "_" not"/")
> or
> "MY_MODULE/PCI_CORE/AD_IO<0>" (where the hierarchical name has been
> extended) or simply "ADIO<0>" where it has been shortened,
> or some similar change.
>
> The first can be fixed by setting the hierarchy separator character (on
> the "Synthesis Properties" dialog); others may be fixable by editing the
> relevant UCF constraints to reflect the actual signal names.
>
> - Brian

Thank you for your good advice... Sounds like I could reduce the
number of errors by fixing the naming in the ucf file and reimplement.
However, there is over 300+ name that need to be fixed and I am not
sure if all of them can be this way...

My thinking is that I need to move the PCI core over to the new
ISE10.1 installation (only webpack with all web updates) from ISE7.1
but I do not know how to do that! I have read in Xilinx documentation
that once you obtain the IP zip file, you need to expand it in C:
\Xilinx\10.1\ISE\coregen\ip\xilinx so I thought instead I can move the
PCI folder from the ISE 7.1 installation folder to C:\Xilinx\10.1\ISE
\coregen\ip\xilinx and run the coregen hoping to detect a new core but
it did not!

Do you think that these error messages are because I have not install
the PCI core in the 10.1 installation although it was able to
synthesis? Thank you all for your great help

On Nov 5, 1:48 am, y.tachw...@gmail.com wrote:
>
> Thank you for your good advice... Sounds like I could reduce the
> number of errors by fixing the naming in the ucf file and reimplement.
> However, there is over 300+ name that need to be fixed and I am not
> sure if all of them can be this way...
>
> My thinking is that I need to move the PCI core over to the new
> ISE10.1 installation (only webpack with all web updates) from ISE7.1
> but I do not know how to do that! I have read in Xilinx documentation
> that once you obtain the IP zip file, you need to expand it in C:
> \Xilinx\10.1\ISE\coregen\ip\xilinx so I thought instead I can move the
> PCI folder from the ISE 7.1 installation folder to C:\Xilinx\10.1\ISE
> \coregen\ip\xilinx and run the coregen hoping to detect a new core but
> it did not!
>
> Do you think that these error messages are because I have not install
> the PCI core in the 10.1 installation although it was able to
> synthesis? Thank you all for your great help

I be surprised if a 7.1 core worked properly in 10.1

I would also be surprised if the web-pack supported the PCI core.

Alex