The JTAG Standard defines a JTAG reset pin, TRST. This pin is little used. All Altera docs (Datasheets, ANs) define this pin but write nothing about its usage. Therefore we did not connect it at all. But we experience problems in the JTAG chain: some EPC chips (especially big ones, like EPC8) almost never finish the Verification phase. I am wondering if this can be due to the unconnected TRST pins? Janos Ero CERN Div. EP
TRST Pin in Altera FPGAs
Started by ●March 2, 2004
Reply by ●March 2, 20042004-03-02
erojr wrote:> The JTAG Standard defines a JTAG reset pin, TRST. This pin is little > used. All Altera docs (Datasheets, ANs) define this pin but write > nothing about its usage. Therefore we did not connect it at all. But we > experience problems in the JTAG chain: some EPC chips (especially big > ones, like EPC8) almost never finish the Verification phase. I am > wondering if this can be due to the unconnected TRST pins? >MaxPlus2 and Quartus produce those *.rpt files. They include an ASCII diagramm showing how the pins are to be connected. Some families don't like open input pins. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Reply by ●March 2, 20042004-03-02
erojr wrote:> > The JTAG Standard defines a JTAG reset pin, TRST. This pin is little > used. All Altera docs (Datasheets, ANs) define this pin but write > nothing about its usage. Therefore we did not connect it at all. But we > experience problems in the JTAG chain: some EPC chips (especially big > ones, like EPC8) almost never finish the Verification phase. I am > wondering if this can be due to the unconnected TRST pins?Absolutely. TRST will reset the JTAG state machine when it floats high. In addition, you should *never* leave a CMOS input floating. When at an intermediate voltage CMOS will draw large currents through the two FETs between power and ground. This can create voltage transients on the power rail inside the chip which can upset other circuits. TRST should either be driven by the JTAG cable, if the emulator supports it, or pulled to Vdd via a resistor; or both actually, so that the input does not float when the cable is not connected. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●March 2, 20042004-03-02
rickman wrote:> erojr wrote: >> >> The JTAG Standard defines a JTAG reset pin, TRST. This pin is little >> used. All Altera docs (Datasheets, ANs) define this pin but write >> nothing about its usage. Therefore we did not connect it at all. But we >> experience problems in the JTAG chain: some EPC chips (especially big >> ones, like EPC8) almost never finish the Verification phase. I am >> wondering if this can be due to the unconnected TRST pins? > > Absolutely. TRST will reset the JTAG state machine when it floats > high. In addition, you should *never* leave a CMOS input floating. > When at an intermediate voltage CMOS will draw large currents through > the two FETs between power and ground. This can create voltage > transients on the power rail inside the chip which can upset other > circuits. TRST should either be driven by the JTAG cable, if the > emulator supports it, or pulled to Vdd via a resistor; or both actually, > so that the input does not float when the cable is not connected.The IEEE 1149.1 specification mandates that the TRST* pin have an internal pullup (if present, it's an optional pin). Pulling the pin low will keep the TAP controller in the TEST-LOGIC-RESET state (device functional). Normally I hardwire the pin to ground to ensure that in the case of any electrical noise or disturbance the chips stay in the operational mode. If there is no TRST* pin on a device, then normally a free running clock (not the system clock) should be sent into TCK with TMS=1. This will logically guarantee that if there are any ooopses, the TAP controller will return to the TEST-LOGIC-RESET state in no more than 5 clock cycles. Note that this is a general statement. Some implementations do not have the mandated pull-up resistor on the TRST*, for instance, and are non-compliant. -- rk
Reply by ●March 3, 20042004-03-03
TRST is often used. erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c21e5p$jnd$1@sunnews.cern.ch>...> The JTAG Standard defines a JTAG reset pin, TRST. This pin is little > used. All Altera docs (Datasheets, ANs) define this pin but write > nothing about its usage. Therefore we did not connect it at all. But we > experience problems in the JTAG chain: some EPC chips (especially big > ones, like EPC8) almost never finish the Verification phase. I am > wondering if this can be due to the unconnected TRST pins? > > Janos Ero > CERN Div. EP
Reply by ●March 4, 20042004-03-04
William Wallace wrote:> TRST is often used.Could you explain this a bit more detailled? TRST is an optional JTAG signal and in JTAG applications you can easily get the same effect using the other signals. Or am I mistaken? Janos Ero CERN Div. EP
Reply by ●March 4, 20042004-03-04
erojr wrote:> > William Wallace wrote: > > TRST is often used. > > Could you explain this a bit more detailled? > > TRST is an optional JTAG signal and in JTAG applications you can easily > get the same effect using the other signals. Or am I mistaken?TRST puts the state machine in a defined state. Most devices also reset the state machine on power up. In addition, if you hold the TMS line high and clock TCK it will return the state machine to the starting state after 5 clock cycles, IIRC. Of course, depending on the implementation, the mechanism that operates the state machine can get fouled up by power glitches or other anomalies. Then the machine may get into a state that operating the TCK line may not control the state. Then you will need a power on or a TRST type reset. I don't know that this is common, but in theory it is possible. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●March 5, 20042004-03-05
rickman wrote:> TRST puts the state machine in a defined state. Most devices also reset > the state machine on power up. In addition, if you hold the TMS line > high and clock TCK it will return the state machine to the starting > state after 5 clock cycles, IIRC. Of course, depending on the > implementation, the mechanism that operates the state machine can get > fouled up by power glitches or other anomalies. Then the machine may > get into a state that operating the TCK line may not control the state. > Then you will need a power on or a TRST type reset. I don't know that > this is common, but in theory it is possible.Thank you for the description. This is exactly that I also found. I do not use the TRST pin but I have never seen a case when the JTAG State Machine did not return to RESET state after 5 clocks. I use the JTAG chain for regular check of the FPGA input pins, not only for programming. The original question was the open TRST pin, but due to the standard internal pullup - I hope this is the case in Altera FPGAs too, but this was not yet confirmed by anybody - the open input must not be the reason for incorrect behavior. Janos Ero
Reply by ●March 5, 20042004-03-05
erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c29ac5$ovb$1@sunnews.cern.ch>...> rickman wrote: > > > TRST puts the state machine in a defined state. Most devices also reset > > the state machine on power up. In addition, if you hold the TMS line > > high and clock TCK it will return the state machine to the starting > > state after 5 clock cycles, IIRC. Of course, depending on the > > implementation, the mechanism that operates the state machine can get > > fouled up by power glitches or other anomalies. Then the machine may > > get into a state that operating the TCK line may not control the state. > > Then you will need a power on or a TRST type reset. I don't know that > > this is common, but in theory it is possible. > > Thank you for the description. This is exactly that I also found. I do not > use the TRST pin but I have never seen a case when the JTAG State Machine > did not return to RESET state after 5 clocks. I use the JTAG chain for > regular check of the FPGA input pins, not only for programming. > > The original question was the open TRST pin, but due to the standard > internal pullup - I hope this is the case in Altera FPGAs too, but this > was not yet confirmed by anybody - the open input must not be the reason > for incorrect behavior. > > Janos EroHi Janos, Altera devices that have a TRST pin have a weak internal pull-up on them. The literature is not very clear on this, so we'll update this. However, not all Altera devices have TRST as it is optional. The EPC8 is one of those without TSRT. It's possible that a floating TRST on some other non-Altera device in the chain would cause such a problem, but I imagine that most JTAG devices would have a weak pull-up on TRST. Another thing to check would be the TCK on the devices in the chain. If one of the devices is getting double-clocked then this would foul up the data passing through the JTAG chain. The tricky part is that a double-clock on any device could cause a problem, not just on the EPC8. Sincerely, Greg Steinke gregs@altera.com Altera Corporation
Reply by ●March 5, 20042004-03-05
erojr wrote:> > rickman wrote: > > > TRST puts the state machine in a defined state. Most devices also reset > > the state machine on power up. In addition, if you hold the TMS line > > high and clock TCK it will return the state machine to the starting > > state after 5 clock cycles, IIRC. Of course, depending on the > > implementation, the mechanism that operates the state machine can get > > fouled up by power glitches or other anomalies. Then the machine may > > get into a state that operating the TCK line may not control the state. > > Then you will need a power on or a TRST type reset. I don't know that > > this is common, but in theory it is possible. > > Thank you for the description. This is exactly that I also found. I do not > use the TRST pin but I have never seen a case when the JTAG State Machine > did not return to RESET state after 5 clocks. I use the JTAG chain for > regular check of the FPGA input pins, not only for programming. > > The original question was the open TRST pin, but due to the standard > internal pullup - I hope this is the case in Altera FPGAs too, but this > was not yet confirmed by anybody - the open input must not be the reason > for incorrect behavior.I don't know about Altera, but I read that TI uses just the opposite convention on their chips. They require a *pulldown* on the board and the JTAG emulator has to have an active pullup to assert the TRST. I assume the TI TRST inputs have no pullup or down. Why not put a TRST pullup on the board to be safe? 10K should do the job and not get in the way. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
