Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell

Hello all,

knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
I convert this into a Xilinx CPLD Macrocell? 

Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
Device (number of Macrocells) would be sufficient?
Haven't found any reference at xilinx or google.

Thanks for any feedback,
Richard

"Eric" <ca9@gmx.de> wrote in message 
news:LeCdnY3PC6QpebvUnZ2dnUVZ_uidnZ2d@giganews.com...
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macrocell?
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.
>
> Thanks for any feedback,
> Richard
>
I assume you don't have access to the i2c RTL, so in that case I would 
download a number of RTL designs from the web and synthesise for both types. 
You can then use the area results to work out a rough conversion factor.

Hans
www.ht-lab.com

Eric wrote:
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macrocell?
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.
>
> Thanks for any feedback,
> Richard

A similar question might be that I know it takes 12 truck loads to
move my cargo from point A to B in the time I need but I can't find a
conversion for going by boat.

The nature of a LUT and a macrocell are rather different.  A design
optimized for one is probably not optimized for the other.  If you
synthesize your code to the target architecture, you'll get a better
estimate by easily a factor of 2 than trying to use a fudge factor.
You may also find code out there optimized for CPLDs.

On Nov 21, 11:41=A0am, "Eric" <c...@gmx.de> wrote:
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how ca=
n
> I convert this into a Xilinx CPLD Macrocell?
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.
>
> Thanks for any feedback,
> Richard

Usually a CPLD macrocell has more combinatorial logic per
flip-flop than a "logic element" from an FPGA.  So a rough way
to look at porting from FPGA to CPLD (macrocell-type, not
the "CPLD" that is really a small non-volatile FPGA like machXO)
is to count the flip-flops in the design and know that you
will need at least that many macrocells.

Remember to count LUTs used as RAM or shift-register as the
appropriate number of flip-flops (usually 16).

By the way 2.25 is an inflated marketing number.  2.0 is the number
of 4-input LUT's and flip-flops in the slice.

Eric wrote:
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macrocell? 
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.

It's very hard to tell, as there isn't any simple conversion factor
you can use.  You need one macrocell for each flip-flop, but if there
were a lot of "logic cells" being used for combinatorial logic, they
might take fewer macrocells because CPLD macrocells can implement
wider functions.  On the other hand, CPLDs tend to be less efficient
for combinatorial functions that have many terms when flattened into
sum-of-products form.