Hi, I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would like to generate a sample rate that is not a integer of this clock and drive a DAC with this sample rate. Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz. This sample rate must be brought to the speed of the clock of DAC to generate it, by interpolating. How to achieve ? It is possible ? Thanks. Kappa.
Generate sample rate ...
Started by ●November 21, 2008
Reply by ●November 21, 20082008-11-21
>I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would like >to generate a sample rate that is not a integer of this clock and drive a >DAC with this sample rate.>Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz.>This sample rate must be brought to the speed of the clock of DAC to >generate it, by interpolating.>How to achieve ? It is possible ?How much do you care about the quality of the signal your DAC is generating? If you want a clean signal, your best bet is to run the DAC off a low jitter osc package. You can make a signal that's close to 9.4 MHz, but it will have some jitter. Google for dds. If you get close enough the error in your source clock will be the major source of error. -- These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●November 21, 20082008-11-21
On Fri, 21 Nov 2008 21:14:16 +0100, "Kappa" wrote:>I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would like >to generate a sample rate that is not a integer of this clock and drive a >DAC with this sample rate. > >Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz. > >This sample rate must be brought to the speed of the clock of DAC to >generate it, by interpolating.Which FPGA? Does it have PLLs or (Xilinx) DCMs? If so you can multiply your clock by M/N where M and N are integers; of course there are limits both on the values of M and N, and on the possible range of output frequencies, but with a little creativity you can probably do what you need. It's all in the data books, or alternatively you can learn a lot simply by running the IP-generator wizard. Another choice is to find out about DDFS (Direct Digital Frequency Synthesis). With this technique you can generate an output frequency with arbitrarily good precision, but the output will suffer jitter of up to one period of the input clock (140MHz, so about 7ns of jitter). More advanced techniques for getting both high resolution and low jitter have been discussed here at length in the past. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●November 21, 20082008-11-21
Hi Hall Murray> How much do you care about the quality of the signal your DAC > is generating?The signal must be good SFDR 60 dB or more.> If you want a clean signal, your best bet is to run the DAC off > a low jitter osc package.Yes, 140 MHz is a OSC with low jitter.> You can make a signal that's close to 9.4 MHz, but it will have > some jitter. Google for dds. If you get close enough the > error in your source clock will be the major source of error.I should not generate an output signal of 9.4 MHz, are able to do this with a DDS, but clocking data at this speed. Kappa.
Reply by ●November 21, 20082008-11-21
On Nov 21, 3:58=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:> On Fri, 21 Nov 2008 21:14:16 +0100, "Kappa" wrote: > >I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would li=ke> >to generate a sample rate that is not a integer of this clock and drive =a> >DAC with this sample rate. > > >Example: Clock 140 MHz --> Sample rate "66Mhz / 7" =3D 9.428571429 MHz. > > >This sample rate must be brought to the speed of the clock of DAC to > >generate it, by interpolating. > > Which FPGA? =A0Does it have PLLs or (Xilinx) DCMs? =A0If so > you can multiply your clock by M/N where M and N are integers; > of course there are limits both on the values of M and N, > and on the possible range of output frequencies, but with a > little creativity you can probably do what you need. > It's all in the data books, or alternatively you can > learn a lot simply by running the IP-generator wizard. > > Another choice is to find out about DDFS (Direct Digital > Frequency Synthesis). =A0With this technique you can generate > an output frequency with arbitrarily good precision, but > the output will suffer jitter of up to one period of the > input clock (140MHz, so about 7ns of jitter). >If you have DDR output registers it's easy enough to make a DDFS with 1/2 cycle jitter or 3.5ns> More advanced techniques for getting both high resolution > and low jitter have been discussed here at length in the past. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.
Reply by ●November 21, 20082008-11-21
Hi Jonathan Bromkey,> Which FPGA?Xilinx FPGA Virtex-4 SX35> Does it have PLLs or (Xilinx) DCMs ?I have some DCM.> If so you can multiply your clock by M/N where M and N are integers; > of course there are limits both on the values of M and N, > and on the possible range of output frequencies, but with a > little creativity you can probably do what you need. > It's all in the data books, or alternatively you can > learn a lot simply by running the IP-generator wizard.I am okay. But if I place a two DCM for example: synthesis attribute CLKFX_MULTIPLY of DCM0 is 2 synthesis attribute CLKFX_DIVIDE of DCM0 is 11 synthesis attribute CLKFX_MULTIPLY of DCM1 is 10 synthesis attribute CLKFX_DIVIDE of DCM1 is 27 actual frequency generated is: 9.427609 MHz (Not exactly frequency) This is OK. Now I have to interpolate order to bring the data to the DAC but how ?> Another choice is to find out about DDFS (Direct Digital > Frequency Synthesis). With this technique you can generate > an output frequency with arbitrarily good precision, but > the output will suffer jitter of up to one period of the > input clock (140MHz, so about 7ns of jitter).I am okay. But the signal is SQUARE WAVE ?> More advanced techniques for getting both high resolution > and low jitter have been discussed here at length in the past.Perhaps I explained badly. Output | | OSC (140 Mhz) --x--> DAC <-- Sample rate data 9.4.... MHz <--FPGA | | | | ----------------------------------------------------- The Sample Rate of 9.4.... MHz is a clock o data. If I put this data to DAC, what I get ? Not the signal that I expect. Kappa.
Reply by ●November 21, 20082008-11-21
On Fri, 21 Nov 2008 21:14:16 +0100 "Kappa" <NO_SPAM_78kappa78@virgilio.it_NO_SPAM> wrote:> Hi, > > I have one clock of 140 MHz. This clock drive a DAC and FPGA. I would > like to generate a sample rate that is not a integer of this clock > and drive a DAC with this sample rate. > > Example: Clock 140 MHz --> Sample rate "66Mhz / 7" = 9.428571429 MHz. > > This sample rate must be brought to the speed of the clock of DAC to > generate it, by interpolating. > > How to achieve ? It is possible ? > > Thanks. > > Kappa. > >Not to ask what may be a stupid question, but why exactly do you want to generate this precise sample rate? -- Rob Gaddi, Highland Technology Email address is currently out of order
Reply by ●November 21, 20082008-11-21
On 21 Nov., 22:21, "Kappa" <NO_SPAM_78kapp...@virgilio.it_NO_SPAM> wrote:> Perhaps I explained badly.Yes, I think so. Your DAC ist running at 140MHz? So probably you should run your signal processing and the data transfer between FPGA and DAC also at 140MHz. Do you want to sent arbitrary PCM coded signals that arrive at 9.4...MHz to the DAC at 140MHz? (google "sample rate conversion", specifically "non integer upsampling") or do you want to use your DAC to output a 9.4...MHz Signal, for example a 9.4MHz sine wave? In that case google "DDS" or "Direct Digital Synthesis" or look for some posts by Peter Alfke in this newgroup. Kolja Sulimma
Reply by ●November 21, 20082008-11-21
Hi Kolja Sulimma,> Your DAC ist running at 140MHz?Yes.> So probably you should run your signal processing and the data > transfer between FPGA and DAC also at 140MHz.Yes. My DAC and FPGA works at 140 MHz.> Do you want to sent arbitrary PCM coded signals that arrive at > 9.4...MHz to the DAC at 140MHz?Yes. My data is at 9.4 MHz Sample Rate.> or do you want to use your DAC to output a 9.4...MHz Signal, for > example a 9.4MHz sine wave? > In that case google "DDS" or "Direct Digital Synthesis" or look for > some posts by Peter Alfke in this newgroup.No this simple for me ... Thanks. Kappa.
Reply by ●November 22, 20082008-11-22
>> How much do you care about the quality of the signal your DAC >> is generating? > >The signal must be good SFDR 60 dB or more.60 dB isn't a lot, but my math skills are good enough to translate that to/from clock jitter.>> If you want a clean signal, your best bet is to run the DAC off >> a low jitter osc package. > >Yes, 140 MHz is a OSC with low jitter.There are two sources of jitter that seem important in this discussion. If you run the clock thrugh the FPGA, that will add some jitter, more if you use the DCM. This comes from things like noise on the power supply rails. If you use something like a DDS to make another clock you can get lots of "interesting" spurs that may or may not be a problem for your application.>> You can make a signal that's close to 9.4 MHz, but it will have >> some jitter. Google for dds. If you get close enough the >> error in your source clock will be the major source of error. > >I should not generate an output signal of 9.4 MHz, are able to do this with >a DDS, but clocking data at this speed.I can't figure out what that means. -- These are my opinions, not necessarily my employer's. I hate spam.
