Hi, For several reasons a need very low jitter on some of my outputs. I was thinking of using LVDS for my I/Os and of course I do not consider using a clock manager. Do you have an idea of the order of magnitude of jitter one can get? What fpga would you recomend for a low cost small design? Cheers Pablo
added jitter on FPGAs
Started by ●November 26, 2008
Reply by ●November 26, 20082008-11-26
"palvarez":> For several reasons a need very low jitter on some of my outputs. I > was thinking of using LVDS for my I/Os and of course I do not consider > using a clock manager. Do you have an idea of the order of magnitude > of jitter one can get? What fpga would you recomend for a low cost > small design?I'm having a similar design constraint for a given project. But in that case, only one external clock-net is jitter-sensitive, so that jitter on the data-lines doesn't matter at all. Gruss Jan Bruns
Reply by ●November 27, 20082008-11-27
On 26 Nov., 19:05, palvarez <pabloalvarezsanc...@gmail.com> wrote:> For several reasons a need very low jitter on some of my outputs. I > was thinking of using LVDS for my I/Os and of course I do not consider > using a clock manager. Do you have an idea of the order of magnitude > of jitter one can get? What fpga would you recomend for a low cost > small design?You have quite a lot of jitter inside an FPGA. We see on the order of 300ps jitter at the output of an Spartan-3 driven by an output flip-flop with a clock driven by a BUFG driven by a DCM. Using the Virtex-5 PLL you should get less jitter. The best Jitter should have an output that uses a regional clock input routed via a BUFIO. Kolja Sulimma
Reply by ●November 27, 20082008-11-27
Hi Kolja, "Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:a48f4020-7f8a-4ce8-949a-e27397d7a370@q9g2000yqc.googlegroups.com...> > Using the Virtex-5 PLL you should get less jitter.Maybe. Maybe not. I do not believe that "PLLs always reduce the jitter inherent on a reference clock." even though Xilinx claim this rubbish in their V5 user guide. (UG190 (v4.3) pg.91). Here's a counter-example. http://www.edn.com/contents/images/6475013.pdf Whatever, the OP's question is too vague to meaningfully answer. He fails to indicate what frequency of jitter he is interested in. Jitter is generally defined from 10Hz upwards, but often 1UI of jitter at 10Hz is inconsequential, but 1UI at 10MHz probably will be a bother. FWIW, common sources of noise which will produce jitter include power supply noise, SSOs, other clocks in the design. Trying to stop these coupling into the outputs when they are all present on a single FPGA may be difficult.> The best Jitter > should have an output that uses a regional clock input routed via a > BUFIO. >I agree. I believe these resources are driven differentially and so will probably have better immunity to noise sources. For even better performance it may be necessary to retime the signals outside of the FPGA. HTH., Syms.
Reply by ●November 28, 20082008-11-28
On Nov 27, 4:40=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:> Hi Kolja, > > "Kolja Sulimma" <ksuli...@googlemail.com> wrote in message > > news:a48f4020-7f8a-4ce8-949a-e27397d7a370@q9g2000yqc.googlegroups.com... > > > > > Using the Virtex-5 PLL you should get less jitter. > > Maybe. Maybe not. I do not believe that "PLLs always reduce the jitter > inherent on a reference clock." even though Xilinx claim this rubbish in > their V5 user guide. (UG190 (v4.3) pg.91). Here's a counter-example.http:=//www.edn.com/contents/images/6475013.pdf> > Whatever, the OP's question is too vague to meaningfully answer. He fails=to> indicate what frequency of jitter he is interested in. Jitter is generall=y> defined from 10Hz upwards, but often 1UI of jitter at 10Hz is > inconsequential, but 1UI at 10MHz probably will be a bother. > > FWIW, common sources of noise which will produce jitter include power sup=ply> noise, SSOs, other clocks in the design. Trying to stop these coupling in=to> the outputs when they are all present on a single FPGA may be difficult.Thanks for all your answers! You are right I was not very clear. What I would like to do is to replace some ECL logic by a small FPGA or PLD. I do not need to be very fast, a 100MHz clock is enough. I am interested in the high frequency jitter and in the low frequency delay changes. I will only have as inputs an LVDS serial link to configure the functionallity, a clock input and a couple of LVDS outputs. Cheers Pablo
Reply by ●March 26, 20092009-03-26
On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez <pabloalvarezsanchez@gmail.com> wrote:>Hi, > >For several reasons a need very low jitter on some of my outputs. I >was thinking of using LVDS for my I/Os and of course I do not consider >using a clock manager. Do you have an idea of the order of magnitude >of jitter one can get? What fpga would you recomend for a low cost >small design? > >Cheers > >PabloHere's a signal that has made three independent non-trivial in/out passes through a Spartan3, plus passed through six external SSI CMOS chips. Total jitter of that whole chain is below 20 ps RMS. ftp://jjlarkin.lmi.net/Jitter3.jpg We were fairly impressed. Spartans are like having a few thousand 10KH ECL gates on a $20 chip. John
Reply by ●March 26, 20092009-03-26
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com...> On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez > <pabloalvarezsanchez@gmail.com> wrote: > >>Hi, >> >>For several reasons a need very low jitter on some of my outputs. I >>was thinking of using LVDS for my I/Os and of course I do not consider >>using a clock manager. Do you have an idea of the order of magnitude >>of jitter one can get? What fpga would you recomend for a low cost >>small design? >> >>Cheers >> >>Pablo > > > Here's a signal that has made three independent non-trivial in/out > passes through a Spartan3, plus passed through six external SSI CMOS > chips. Total jitter of that whole chain is below 20 ps RMS. > > ftp://jjlarkin.lmi.net/Jitter3.jpg > > > We were fairly impressed. Spartans are like having a few thousand 10KH > ECL gates on a $20 chip. > > John >I've just built a fractional-N synthesizer using a Spartan 3. The reference frequency comes from an LVDS-output crystal oscillator. The VCO frequency is fed into the opposite side of the FPGA using an LVDS-output comparator and the (AD9901 style) PFD output from the FPGA to the loop filter is also LVDS on a third physical side. Inside the FPGA, the VCO divider and reference divider are on local clocks confined to small regions around the pads where they enter. BUFGCE primitives are used to gate the clocks so I only send edges over the global clock network when a divider resets. The AD9901 PFD ensures that the VCO and reference divider outputs are 180 degrees out of phase. Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84 CPLD. It worked quite well, but there was some interation between the VCO and reference frequencies which caused integer-N boundary spurs. I see no trace of these spurs on my new Spartan 3 design, and the phase noise is much lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I haven't finished tweaking things yet. They say don't attempt analogue functions in FPGAs; but it seems to work remarkably well in the Spartan 3, which is fully static when I'm not clocking it.
Reply by ●March 26, 20092009-03-26
On Thu, 26 Mar 2009 19:34:22 -0000, "Andrew Holme" <ah@nospam.co.uk> wrote:> >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:nhfns4lrd245pvu2lt4pnn03lio466j5ti@4ax.com... >> On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez >> <pabloalvarezsanchez@gmail.com> wrote: >> >>>Hi, >>> >>>For several reasons a need very low jitter on some of my outputs. I >>>was thinking of using LVDS for my I/Os and of course I do not consider >>>using a clock manager. Do you have an idea of the order of magnitude >>>of jitter one can get? What fpga would you recomend for a low cost >>>small design? >>> >>>Cheers >>> >>>Pablo >> >> >> Here's a signal that has made three independent non-trivial in/out >> passes through a Spartan3, plus passed through six external SSI CMOS >> chips. Total jitter of that whole chain is below 20 ps RMS. >> >> ftp://jjlarkin.lmi.net/Jitter3.jpg >> >> >> We were fairly impressed. Spartans are like having a few thousand 10KH >> ECL gates on a $20 chip. >> >> John >> > >I've just built a fractional-N synthesizer using a Spartan 3. The reference >frequency comes from an LVDS-output crystal oscillator. The VCO frequency >is fed into the opposite side of the FPGA using an LVDS-output comparator >and the (AD9901 style) PFD output from the FPGA to the loop filter is also >LVDS on a third physical side. > >Inside the FPGA, the VCO divider and reference divider are on local clocks >confined to small regions around the pads where they enter. BUFGCE >primitives are used to gate the clocks so I only send edges over the global >clock network when a divider resets. The AD9901 PFD ensures that the VCO >and reference divider outputs are 180 degrees out of phase. > >Some years ago, I built a cruder fractional-N synth using a 5V Altera PLCC84 >CPLD. It worked quite well, but there was some interation between the VCO >and reference frequencies which caused integer-N boundary spurs. I see no >trace of these spurs on my new Spartan 3 design, and the phase noise is much >lower. I'm seeing around -95 dBc/Hz at 100 Hz offsets at the moment; and I >haven't finished tweaking things yet. > > >They say don't attempt analogue functions in FPGAs; but it seems to work >remarkably well in the Spartan 3, which is fully static when I'm not >clocking it. > >The Spartan LVDS inputs are pretty good r-r comparators. And you can make lots of good, cheap delta-sigma dacs from an FPGA. You can do cool analog things with FPGAs. You can also get into a heap of trouble. John
Reply by ●March 26, 20092009-03-26
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:>On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez ><pabloalvarezsanchez@gmail.com> wrote: > >>Hi, >> >>For several reasons a need very low jitter on some of my outputs. I >>was thinking of using LVDS for my I/Os and of course I do not consider >>using a clock manager. Do you have an idea of the order of magnitude >>of jitter one can get? What fpga would you recomend for a low cost >>small design? >> >>Cheers >> >>Pablo > > >Here's a signal that has made three independent non-trivial in/out >passes through a Spartan3, plus passed through six external SSI CMOS >chips. Total jitter of that whole chain is below 20 ps RMS. > >ftp://jjlarkin.lmi.net/Jitter3.jpgI presume this is without routing the clock through the DCM :-) -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... "If it doesn't fit, use a bigger hammer!" --------------------------------------------------------------
Reply by ●March 26, 20092009-03-26
On Thu, 26 Mar 2009 23:02:35 GMT, nico@puntnl.niks (Nico Coesel) wrote:>John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Wed, 26 Nov 2008 10:05:06 -0800 (PST), palvarez >><pabloalvarezsanchez@gmail.com> wrote: >> >>>Hi, >>> >>>For several reasons a need very low jitter on some of my outputs. I >>>was thinking of using LVDS for my I/Os and of course I do not consider >>>using a clock manager. Do you have an idea of the order of magnitude >>>of jitter one can get? What fpga would you recomend for a low cost >>>small design? >>> >>>Cheers >>> >>>Pablo >> >> >>Here's a signal that has made three independent non-trivial in/out >>passes through a Spartan3, plus passed through six external SSI CMOS >>chips. Total jitter of that whole chain is below 20 ps RMS. >> >>ftp://jjlarkin.lmi.net/Jitter3.jpg > >I presume this is without routing the clock through the DCM :-)Yes! One of the three FPGA inputs is in fact a global clock, but it's not multiplied or anything. In another mode, we do double a 40 MHz clock to 80 in a DCM. That adds about 80 ps p-p jitter, because it wiggles alternate 80 MHz clock edges. John
