Xiic with low lvl interrupts

Hello everybody ...

Im trying to code an isr for the xiic Ip from Xilinx EDK.
I did everything like tht documentation says but it wont work.

i get an interrupt when the modul is adressed as slave and its the AAS
irq.
After i get it, ill reset the interrupt that it is acknowledged but it
wont work ..

thats how my isr looks like ...


void iic_1_handler(void * baseaddr_p) {

 XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK, 0x03);

   if(XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR) & XIIC_INTR_AAS_MASK){
     XIIC_GINTR_DISABLE(XPAR_XPS_IIC_1_BASEADDR);
     XIic_mWriteReg
(XPAR_XPS_IIC_1_BASEADDR,XIIC_IIER_OFFSET,XIIC_READ_IISR
(XPAR_XPS_IIC_1_BASEADDR));
     XIIC_GINTR_ENABLE(XPAR_XPS_IIC_1_BASEADDR);
     XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK,
XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR));

   }

}
does anyone have an working controll flow?

thx for help

Not sure if it's what you are looking for, but Avnet has an XIIC
example with interrupts connected to a TI Temp Sensor.

www.em.avnet.com/spartan3a-evl --> Support Files & Downloads -->
MicroBlaze IIC Temperature Sensor

Bryan

On Dec 6, 8:06=A0am, simax <opitz.fr...@googlemail.com> wrote:
> Hello everybody ...
>
> Im trying to code an isr for the xiic Ip from Xilinx EDK.
> I did everything like tht documentation says but it wont work.
>
> i get an interrupt when the modul is adressed as slave and its the AAS
> irq.
> After i get it, ill reset the interrupt that it is acknowledged but it
> wont work ..
>
> thats how my isr looks like ...
>
> void iic_1_handler(void * baseaddr_p) {
>
> =A0XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK, 0x03);
>
> =A0 =A0if(XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR) & XIIC_INTR_AAS_MASK){
> =A0 =A0 =A0XIIC_GINTR_DISABLE(XPAR_XPS_IIC_1_BASEADDR);
> =A0 =A0 =A0XIic_mWriteReg
> (XPAR_XPS_IIC_1_BASEADDR,XIIC_IIER_OFFSET,XIIC_READ_IISR
> (XPAR_XPS_IIC_1_BASEADDR));
> =A0 =A0 =A0XIIC_GINTR_ENABLE(XPAR_XPS_IIC_1_BASEADDR);
> =A0 =A0 =A0XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK,
> XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR));
>
> =A0 =A0}
>
> }
>
> does anyone have an working controll flow?
>
> thx for help