Hi,
I know DFF is:
module DFF(d,clk,q) ;
input d, clk ;
output reg q ;
always @(posedge clk)
q<= d ;
endmodule
Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?
The implemented circuit MUST WORK AS FOLLOWS:
module DFFR(d,clk,r, q) ;
input d, clk,r ;
output reg q ;
always @(posedge clk or posedge r)
if (r) q <= 0 ;
else q<= d ;
endmodule
Please give the code or diagram. I am curious about this.
Sant
DFFR using DFF (only, may be extra gates)
Started by ●December 23, 2008
Reply by ●December 23, 20082008-12-23
santhosh_h_98@yahoo.com wrote:> Hi, > > I know DFF is: > > module DFF(d,clk,q) ; > input d, clk ; > output reg q ; > > always @(posedge clk) > q<= d ; > endmodule > > Now I need to implement ASYNCHRONOUS RESET flip flop > using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ? > > The implemented circuit MUST WORK AS FOLLOWS: > > module DFFR(d,clk,r, q) ; > input d, clk,r ; > output reg q ; > > always @(posedge clk or posedge r) > if (r) q <= 0 ; > else q<= d ; > endmodule > > Please give the code or diagram. I am curious about this. >Well actually that'll cost logic in the clock path. You'll most likely have to create an own clock clk_dffr which is clk or rst; and you'll need d_dffr which will be d and not rst. That should solve the task (though I'm not happy about that solution, but no better one came to my mind).> SantRegards, Lorenz
Reply by ●December 23, 20082008-12-23
On Dec 23, 11:54=A0am, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote:> santhosh_h...@yahoo.com wrote: > > Hi, > > > I know DFF is: > > > module DFF(d,clk,q) ; > > =A0 =A0 =A0input d, clk ; > > =A0 =A0 =A0output reg q ; > > > =A0 =A0 =A0always @(posedge clk) > > =A0 =A0 =A0 =A0 =A0 =A0q<=3D d ; > > endmodule > > > Now I need to implement ASYNCHRONOUS RESET flip flop > > using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ? > > > The implemented circuit MUST WORK AS FOLLOWS: > > > module DFFR(d,clk,r, q) ; > > =A0 =A0 =A0input d, clk,r ; > > =A0 =A0 =A0output reg q ; > > > =A0 =A0 =A0always @(posedge clk or posedge r) > > =A0 =A0 =A0 =A0 =A0 if (r) q <=3D 0 ; > > =A0 =A0 =A0 =A0 =A0 else =A0q<=3D d ; > > endmodule > > > Please give the code or diagram. I am curious about this. > > Well actually that'll cost logic in the clock path. You'll most likely > have to create an own clock clk_dffr which is clk or rst; and you'll > need d_dffr which will be d and not rst. > > That should solve the task (though I'm not happy about that solution, > but no better one came to my mind). > > > Sant > > Regards, > > LorenzEven then you would need to ensure adequate setup time on the D input when resetting. Assuming D was otherwise high, d_dffr and clk_dffr would change at the same time unless you made extra delay in the clock path. And of course you need to make sure that your path from the standard D input still has hold time after all of the gating... Good luck, Gabor
Reply by ●December 23, 20082008-12-23
>> > Now I need to implement ASYNCHRONOUS RESET flip flop >> > using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ? >> >> > The implemented circuit MUST WORK AS FOLLOWS: >> >> > module DFFR(d,clk,r, q) ; >> > � � �input d, clk,r ; >> > � � �output reg q ; >> >> > � � �always @(posedge clk or posedge r) >> > � � � � � if (r) q <= 0 ; >> > � � � � � else �q<= d ; >> > endmodule >> >> > Please give the code or diagram. I am curious about this.The thing I'm curious about is WHY? Gabor is right about the extreme difficulty of getting something that works correctly if you try to gate reset and clock together. If you're allowed any amount of combinational logic in addition to DFF, which I assume is the case, then you could consider this idea, (c)2008 Santa's Elves, to be enjoyed in moderation with a vomit-bag handy: module DFFR(input d, clk, r, output q); // wire d_int, q_int, flipper; // // Here's the main FF. Its output is inverted // if necessary to give reset behaviour. DFF data_ff(.d(d_int), .clk(clk), .q(q_int)); assign q = q_int ^ flipper; // // The second FF captures the data FF's output // when reset happens, and uses that captured // value to invert the main FF's output if necessary. DFF flipper_ff(.d(q_int), .clk(r), .q(flipper); // // Finally, we invert the D input to the main FF // to match the inversion of its output. But we // also disable clocking of this FF while reset // is active, so that we don't need to worry about // the reset value at any time other than (posedge r). assign d_int = r? q_int: d ^ flipper; // endmodule This is still exposed to a race between active edges of clock and reset, but otherwise I think it works; and it doesn't corrupt the hold time behaviour of the main (data_ff) flop. Actually, on mature reflection I think this one is (c)2008 The Grinch. Season's Greetings to all :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●December 23, 20082008-12-23
On Dec 23, 1:20=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:> >> > Now I need to implement ASYNCHRONOUS RESET flip flop > >> > using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ? > > >> > The implemented circuit MUST WORK AS FOLLOWS: > > >> > module DFFR(d,clk,r, q) ; > >> > =A0 =A0 =A0input d, clk,r ; > >> > =A0 =A0 =A0output reg q ; > > >> > =A0 =A0 =A0always @(posedge clk or posedge r) > >> > =A0 =A0 =A0 =A0 =A0 if (r) q <=3D 0 ; > >> > =A0 =A0 =A0 =A0 =A0 else =A0q<=3D d ; > >> > endmodule > > >> > Please give the code or diagram. I am curious about this. > > The thing I'm curious about is WHY? > > Gabor is right about the extreme difficulty of getting > something that works correctly if you try to gate reset > and clock together. > > If you're allowed any amount of combinational logic > in addition to DFF, which I assume is the case, then > you could consider this idea, (c)2008 Santa's Elves, > to be enjoyed in moderation with a vomit-bag handy: > > module DFFR(input d, clk, r, output q); > =A0 // > =A0 wire d_int, q_int, flipper; > =A0 // > =A0 // Here's the main FF. =A0Its output is inverted > =A0 // if necessary to give reset behaviour. > =A0 DFF data_ff(.d(d_int), .clk(clk), .q(q_int)); > =A0 assign q =3D q_int ^ flipper; > =A0 // > =A0 // The second FF captures the data FF's output > =A0 // when reset happens, and uses that captured > =A0 // value to invert the main FF's output if necessary. > =A0 DFF flipper_ff(.d(q_int), .clk(r), .q(flipper); > =A0 // > =A0 // Finally, we invert the D input to the main FF > =A0 // to match the inversion of its output. =A0But we > =A0 // also disable clocking of this FF while reset > =A0 // is active, so that we don't need to worry about > =A0 // the reset value at any time other than (posedge r). > =A0 assign d_int =3D r? q_int: d ^ flipper; > =A0 // > endmodule > > This is still exposed to a race between active edges > of clock and reset, but otherwise I think it works; > and it doesn't corrupt the hold time behaviour of the > main (data_ff) flop. > > Actually, on mature reflection I think this one is > (c)2008 The Grinch. > > Season's Greetings to all :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Wow! My head is spinning! It seems to me if you want to use the gated Q approach, you don't really need a "flipper" but only an AND gate since reset can only drive the Q output low. If you made an internal reset signal, on while "r" is asserted and held until the data flip-flop Q output is low, you can gate this into the d input of the data flip-flop as a synchronous reset, and also gate it with Q to make the reset appear asynchronous. You wouldn't need a proper D flip-flop for the reset signal, just an implied latch like: r_int =3D r | r_int & q_int; then d_int =3D d & !r_int; q =3D q_int & !r_int; Cheers, Gabor
Reply by ●December 23, 20082008-12-23
I>Gabor is right about the extreme difficulty of getting >something that works correctly if you try to gate reset >and clock together. > >If you're allowed any amount of combinational logic >in addition to DFF, which I assume is the case, then >you could consider this idea, (c)2008 Santa's Elves, >to be enjoyed in moderation with a vomit-bag handy:If you have unlimited gates, why not just ignore the DFF? Old data books gave gate level diagrams for things like FFs. Here is an example: http://focus.ti.com/lit/ds/symlink/sn74ls74a.pdf An edge triggered FF is two latches. A latch is a pair of cross coupled gates. Set/Reset are just another term into some of the gates. -- These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●December 23, 20082008-12-23
On Tue, 23 Dec 2008 18:20:50 +0000, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:>This is still exposed to a race between active edges >of clock and reset, but otherwise I think it works; >and it doesn't corrupt the hold time behaviour of the >main (data_ff) flop.How is this any different from a DFFR ie a DFF with built-in async reset? One has to meet the reset removal timing in a DFFR which is the same problem with your solution above. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●December 23, 20082008-12-23
On Tue, 23 Dec 2008 11:12:45 -0800 (PST), gabor <gabor@alacron.com> wrote:>It seems to me if you want to use the gated Q approach, you >don't really need a "flipper" but only an AND gate since >reset can only drive the Q output low. If you made an >internal reset signal, on while "r" is asserted and >held until the data flip-flop Q output is low, you can >gate this into the d input of the data flip-flop as >a synchronous reset, and also gate it with Q to make the >reset appear asynchronous. You wouldn't need a proper >D flip-flop for the reset signal, just an implied >latch like: > >r_int = r | r_int & q_int; > >then > >d_int = d & !r_int; > >q = q_int & !r_int;This doesn't solve the problem perfectly. A real async reset flop doesn't need a clock edge to reset the internal state of the flop so if a reset arrives and leaves before any clock edges appear the Q of the flop changes to and stays at 0. In the case above the you have no control over q_int which is presumably X in this condition so when you remove reset q will go back to X which is what the async reset was trying to solve after all. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●December 23, 20082008-12-23
On Dec 23, 3:25=A0pm, Muzaffer Kal <k...@dspia.com> wrote:> On Tue, 23 Dec 2008 11:12:45 -0800 (PST), gabor <ga...@alacron.com> > wrote: > > > > >It seems to me if you want to use the gated Q approach, you > >don't really need a "flipper" but only an AND gate since > >reset can only drive the Q output low. =A0If you made an > >internal reset signal, on while "r" is asserted and > >held until the data flip-flop Q output is low, you can > >gate this into the d input of the data flip-flop as > >a synchronous reset, and also gate it with Q to make the > >reset appear asynchronous. =A0You wouldn't need a proper > >D flip-flop for the reset signal, just an implied > >latch like: > > >r_int =3D r | r_int & q_int; > > >then > > >d_int =3D d & !r_int; > > >q =3D q_int & !r_int; > > This doesn't solve the problem perfectly. A real async reset flop > doesn't need a clock edge to reset the internal state of the flop so > if a reset arrives and leaves before any clock edges appear the Q of > the flop changes to and stays at 0. In the case above the you have no > control over q_int which is presumably X in this condition so when you > remove reset q will go back to X which is what the async reset was > trying to solve after all. > > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.comWell actually that is why r_int is held until q_int goes low. This guarantees that the next clock edge after reset also clocks the Q low. The down side to this of course is that it doesn't actually model a D flip-flop with async reset, which could possibly go high on the first edge after reset is released.
Reply by ●December 23, 20082008-12-23
On Tue, 23 Dec 2008 12:46:45 -0800 (PST), Gabor <gabor@alacron.com> wrote:>On Dec 23, 3:25�pm, Muzaffer Kal <k...@dspia.com> wrote: >> On Tue, 23 Dec 2008 11:12:45 -0800 (PST), gabor <ga...@alacron.com> >> wrote: >> >> >> >> >It seems to me if you want to use the gated Q approach, you >> >don't really need a "flipper" but only an AND gate since >> >reset can only drive the Q output low. �If you made an >> >internal reset signal, on while "r" is asserted and >> >held until the data flip-flop Q output is low, you can >> >gate this into the d input of the data flip-flop as >> >a synchronous reset, and also gate it with Q to make the >> >reset appear asynchronous. �You wouldn't need a proper >> >D flip-flop for the reset signal, just an implied >> >latch like: >> >> >r_int = r | r_int & q_int; >> >> >then >> >> >d_int = d & !r_int; >> >> >q = q_int & !r_int; >> >> This doesn't solve the problem perfectly. A real async reset flop >> doesn't need a clock edge to reset the internal state of the flop so >> if a reset arrives and leaves before any clock edges appear the Q of >> the flop changes to and stays at 0. In the case above the you have no >> control over q_int which is presumably X in this condition so when you >> remove reset q will go back to X which is what the async reset was >> trying to solve after all. >> >> Muzaffer Kal >> >> DSPIA INC. >> ASIC/FPGA Design Services >> http://www.dspia.com > >Well actually that is why r_int is held until q_int goes >low. This guarantees that the next clock edge after reset >also clocks the Q low. The down side to this of course >is that it doesn't actually model a D flip-flop with >async reset, which could possibly go high on the first >edge after reset is released.I think the down side is a little more than that. If q_int is X (which is what one should expect for a flop with no async controls), "r_int & q_int" is also X. So when r goes high then low, r_int is 1 then X. I don't think you're getting the latching affect you're looking for; in Verilog simulation anyway. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
