VHDL: Process vs concurrent stataments?

Hi all,
I'm a VHDL beginner and I've a trouble with a simple VHDL piece code.

Writing the same thing in two ways that (appearently to me) seem to be
the same,
produce different resuls.

In one case the code is synthesized, in the other it is not.

This is the first piece of code, written as a process.
It is well synthesized:

sample_parallel_data : process(SYS_CK_IN,RESET) begin
		if(RESET = '0') then
			tx_data <= (others => '0');
		elsif(rising_edge(SYS_CK_IN)) then
			if(counter mod (SYS_CK_RATIO/2) = 0) then
				if(last_lr_ck = '1') then
					tx_data <= "0" & DATA_R(IN_WIDTH-1 downto 0) & "0000000";
				else
					tx_data <= "0" & DATA_L(IN_WIDTH-1 downto 0) & "0000000";
				end if;
			else
				tx_data <= tx_data(BITXCH-2 downto 0) & '0'; --shift data left
			end if;
		end if;
	end process;

Now there's the some code, written as a concurrent statement... this
one reports me the error
"Signal tx_data cannot be synthesized, bad synchronous description."

tx_data <=
		(others => '0') when RESET='0'
	else
		'0' & DATA_L(IN_WIDTH-1 downto 0) & "0000000"
		when rising_edge(SYS_CK_IN)
		and (counter mod (SYS_CK_RATIO/2) = 0)
		and last_lr_ck = '1'
	else
		'0' & DATA_R(IN_WIDTH-1 downto 0) & "0000000"
		when rising_edge(SYS_CK_IN)
		and (counter mod (SYS_CK_RATIO/2) = 0)
		and last_lr_ck = '0'
	else
		tx_data(BITXCH-2 downto 0) & '0'
		when rising_edge(SYS_CK_IN);


Why are these piece of code different?
It appear the same thing in my mind !

Thanks all,
Primiano Tucci
--
http://www.primianotucci.com/

I forgot some details,

tx_data is a signal
  signal signal tx_data : std_logic_vector(BITXCH-1 downto 0);

DATA_L and DATA_R are two input ports
	DATA_L : in std_logic_vector(IN_WIDTH-1 downto 0);
	DATA_R : in std_logic_vector(IN_WIDTH-1 downto 0);

BITXCH is a constant = 32
IN_WIDTH is a constant = 24

Thanks
Primiano Tucci
--
http://www.primianotucci.com/

On Sun, 18 Jan 2009 12:59:55 -0800 (PST), p.tucci wrote:

>Writing the same thing in two ways that (appearently to me) seem to be
>the same, produce different resuls.
>
>In one case the code is synthesized, in the other it is not.
>
>This is the first piece of code, written as a process.
>It is well synthesized:

Yes, because it follows the standard synthesis template
that all synth tools understand.

> sample_parallel_data : process(SYS_CK_IN,RESET) begin
>   if(RESET = '0') then
>     tx_data <= (others => '0');
>   elsif(rising_edge(SYS_CK_IN)) then
      [... do interesting things to tx_data...]
>   end if;
>  end process;

>Now there's the some code, written as a concurrent statement... this
>one reports me the error
>"Signal tx_data cannot be synthesized, bad synchronous description."

>tx_data <=
>		(others => '0') when RESET='0'
>	else
>		'0' & DATA_L(IN_WIDTH-1 downto 0) & "0000000"
>		when rising_edge(SYS_CK_IN)
>		and (counter mod (SYS_CK_RATIO/2) = 0)
>		and last_lr_ck = '1'
>	else
>		'0' & DATA_R(IN_WIDTH-1 downto 0) & "0000000"
>		when rising_edge(SYS_CK_IN)
>		and (counter mod (SYS_CK_RATIO/2) = 0)
>		and last_lr_ck = '0'
>	else
>		tx_data(BITXCH-2 downto 0) & '0'
>		when rising_edge(SYS_CK_IN);

I agree with you that the two pieces of code should simulate
in the same way (I haven't checked the details, but it certainly
looks about right).  However, the second example has at least
two problems that would surely cause many synthesis tools to fail:
(1) You have three distinct "else" branches, and EACH BRANCH
    has a clock edge test in it.  Synthesis tools usually expect
    the clock edge test to be at the outermost level of nesting.
(2) In two of those three branches, you have other logic ANDed
    with the clock edge test.  Again this doesn't match the
    synthesisable template, and many (maybe even "all") synth
    tools will reject it.

I'm not promising, but you MAY find that the following form
synthesises OK:

 tx_data <= 
      (others => '0') 
            when RESET='0'
    else
      func(tx_data, DATA_L, DATA_R, last_lr_ck) 
            when rising_edge(SYS_CK_IN);

where "func()" is a function that performs all the 
necessary next-state logic - essentially, the body
of the clocked branch of your first, successful process.

But it's far better to stick to the standard template,
especially in cases like this where there is no benefit
to using a different style.

~~~~~~~~~~~~

Be aware that you'll probably get a better response 
on comp.lang.vhdl for pure VHDL questions like this.
-- 
Jonathan Bromley, Consultant

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