Hi all, I need to generate a squarewave in increments of 2 Hz.(Accuracy should be 1Hz). I thought I use a PIC18 and a AD9833 but I keep thinking about the MAX3000A. I think the implementation should be simpler on it but I just can't get started thinking that it is not going to work. I thought I use an external oscillator and divide the freq. down (with the MAX3000A) to what a set of BCD (8 to 12 bits) switches are set to. Last time I use a MAX3000A I drew the schematic but this time I thought Verilog HDL would seem simpler. Any thought on it? Comments/suggestions welcome. Thanks
Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
Started by ●January 22, 2009
Reply by ●January 23, 20092009-01-23
On Fri, 23 Jan 2009 03:27:05 GMT, "Rodo" <noway@youwish.com> wrote:>Hi all, > >I need to generate a squarewave in increments of 2 Hz.(Accuracy should be >1Hz). I thought I use a PIC18 and a AD9833 but I keep thinking about the >MAX3000A. I think the implementation should be simpler on it but I just >can't get started thinking that it is not going to work. I thought I use an >external oscillator and divide the freq. down (with the MAX3000A) to what a >set of BCD (8 to 12 bits) switches are set to. Last time I use a MAX3000A I >drew the schematic but this time I thought Verilog HDL would seem simpler. >Any thought on it?Direct digital synthesis (DDS) is easy to implement, and can give you the resolution you need with no difficulty - PROVIDED you can tolerate the jitter of +/- one system clock period on the generated edges. And yes, it is definitely easier in HDL. If this is for timing of real-world activity such as motion control, DDS is certainly a good method. If you need a very predictable frequency spectrum, free of the spurious components created by jitter on the output edges, then you may need to try some other method. It sounds as though you only want to go up to a few kHz, so there are many possible approaches available. Tell us more! Just a few rough numbers to get these things into perspective: Suppose you have a 30MHz system clock, giving 33ns of jitter on your DDS square wave's edges. If the application is audio-related, that corresponds to a physical shift of about 0.01mm in the distance from source to "listener", or a phase shift of about 0.01 degree in a 1kHz tone. Probably not a big deal. On the other hand, it corresponds to a distance of nearly 10 metres in an optical system, probably rendering it useless for LIDAR or other measurement applications. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●January 23, 20092009-01-23
I looked at the DDS info in the Altera site but I didn't see any mention that it was for the CPLDs. They talk about a megacore function and FPGAs. Can this be used in a MAX3000? I'm not doing anything fancy but cost and current consumption are an issue. I'd like to use as low a frequency I can to run the CPLD. Do you have any info on implementing a DDS? Thanks "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:vsajn45uejgjqm0r2lo8vjdij6kt01c7e6@4ax.com...> On Fri, 23 Jan 2009 03:27:05 GMT, "Rodo" <noway@youwish.com> wrote: > >>Hi all, >> >>I need to generate a squarewave in increments of 2 Hz.(Accuracy should be >>1Hz). I thought I use a PIC18 and a AD9833 but I keep thinking about the >>MAX3000A. I think the implementation should be simpler on it but I just >>can't get started thinking that it is not going to work. I thought I use >>an >>external oscillator and divide the freq. down (with the MAX3000A) to what >>a >>set of BCD (8 to 12 bits) switches are set to. Last time I use a MAX3000A >>I >>drew the schematic but this time I thought Verilog HDL would seem simpler. >>Any thought on it? > > Direct digital synthesis (DDS) is easy to implement, > and can give you the resolution you need with no > difficulty - PROVIDED you can tolerate the jitter > of +/- one system clock period on the generated edges. > And yes, it is definitely easier in HDL. > > If this is for timing of real-world activity such > as motion control, DDS is certainly a good method. > If you need a very predictable frequency spectrum, > free of the spurious components created by jitter > on the output edges, then you may need to try some > other method. It sounds as though you only want to > go up to a few kHz, so there are many possible > approaches available. Tell us more! > > Just a few rough numbers to get these things into > perspective: Suppose you have a 30MHz system > clock, giving 33ns of jitter on your DDS square > wave's edges. If the application is audio-related, > that corresponds to a physical shift of about 0.01mm > in the distance from source to "listener", or a phase > shift of about 0.01 degree in a 1kHz tone. Probably > not a big deal. On the other hand, it corresponds to > a distance of nearly 10 metres in an optical system, > probably rendering it useless for LIDAR or other > measurement applications. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.
Reply by ●January 23, 20092009-01-23
"Rodo" <noway@youwish.com> wrote in message news:Dvtel.1551$Aw2.414@nwrddc02.gnilink.net...>I looked at the DDS info in the Altera site but I didn't see any mention >that it was for the CPLDs. They talk about a megacore function and FPGAs. >Can this be used in a MAX3000? > > I'm not doing anything fancy but cost and current consumption are an > issue. I'd like to use as low a frequency I can to run the CPLD. Do you > have any info on implementing a DDS? > > Thanks > >Do a web search for DDS. You'll find all the info you need. I used info from Google to design a DDS generator for a microcontroller. You can do the same. If you can't then you should try a different career. Bob -- == All google group posts are automatically deleted due to spam ==
Reply by ●January 23, 20092009-01-23
>I looked at the DDS info in the Altera site but I didn't see any mention >a squarewave in increments of 2 Hz.Hi, I don't think you need to go the DDS path if what you are planning is divide a clock to lower frequencies. You can use just a modulo adder that runs on your input clock and increments by a value chosen for each required frequency(NCO,numerically controlled oscillator), the output clock can be taken directly from the MSB of adder, thus: output frequency = input frequency * increment/modulus Accuracy can be as low as micro Hz if you choose a wide adder(high value of modulus and increment). You will only get a regular clock if the ratio input frequency/output frequency is integer otherwise you will end up with repeated iregularity. kadhiem
Reply by ●January 24, 20092009-01-24
On Fri, 23 Jan 2009 03:27:05 GMT, "Rodo" <no...@youwish.com> wrote: >Hi all, >I need to generate a squarewave in increments of 2 Hz.(Accuracy should be >1Hz). I thought I use a PIC18 and a AD9833 but I keep thinking about the >MAX3000A. I think the implementation should be simpler on it but I just >can't get started thinking that it is not going to work. I thought I use an >external oscillator and divide the freq. down (with the MAX3000A) to what a >set of BCD (8 to 12 bits) switches are set to. Last time I use a MAX3000A I >drew the schematic but this time I thought Verilog HDL would seem simpler. >Any thought on it? DDS is one solution, but may not map too well to BCD switches. Google CD4527 / HEF4527 for a BCD rate multiplier example. This is effectively a picket fence pulse density modulation, that gives an average Frequency. They can also be used as DAC's Like DDS, it has some jitter, so you start from a high clock, and then do a 12-16 bit BCD Rate Multiplier, and then as much divider following that as practical. Each BCD digit needs 4 bits(MCells) counter + 1 Mcell as Combiner. In a MAX3000, with 32 MCells, you might choose 1999 FS for 15+2 bits,and N/2000 in the BCD block, then 16.384MHz lets you divide by 8192 and you have used 30 macrocells. Or, you might like 9999 FS, and N/10000, (20MC) then 2048 yields 20.48MHz, and 31 Macrocells. The post-divider integrates jitter, and does not have to be 2^N - eg 16MHz divided by 1600, gives '9999' entry into your BCD frequency set. -jg
Reply by ●January 24, 20092009-01-24
"Rodo" <no...@youwish.com> wrote in message >I looked at the DDS info in the Altera site but I didn't see any mention >that it was for the CPLDs. They talk about a megacore function and FPGAs. >Can this be used in a MAX3000? > I'm not doing anything fancy but cost and current consumption are an > issue. I'd like to use as low a frequency I can to run the CPLD. Do you > have any info on implementing a DDS? MAX3000 is not what anyone would call Low Current .. :) Better are Atmel ATF1502BE, Lattice 4032ZE, Xilinx XC2C32A The lower the clock speed, the more the jitter, so you will need to decide what matters there (ie how much spectral width can you tolerate ?) To minimize power, use only as many bits as you need. eg 2MHz gives 0.5u Clk Quantize, and a BCD rate Multiplier divide of 1000, (see my other post) and probably your 2MHz oscillator will draw more than the ZeroPower CPLD !! .
Reply by ●January 24, 20092009-01-24
On Fri, 23 Jan 2009 19:53:29 -0600, "kadhiem_ayob" wrote:>I don't think you need to go the DDS path if what you are planning is >divide a clock to lower frequencies.The terminology for DDS (direct digital synthesis) and NCO (numerically controlled oscillator) is not very well defined, but I was probably wrong to mention DDS when in fact I was talking about a phase-accumulator square wave generator, just as kadhiem describes. kadhiem's scheme works only if the divisor (modulus) is an exact power of 2. With a little more effort it's easy to get N/M frequency multiplication/division for arbitrary N,M. But the jitter problem remains. DDS would allow you to generate an approximate sinewave at the desired frequency. This could be low-pass filtered and then squared using an analogue comparator, giving significantly better jitter performance than a simple square-wave phase accumulator. Unfortunately the OP still hasn't said what he really needs, but instead has just complained that he can't find how to do it - despite many sensible and useful suggestions. I tried a simple phase-accumulator implementation in a MAX3000, and discovered to my horror how expensive it is to construct a wide adder in these devices; the synthesis tool I tried can fit only a 14-bit accumulator in a 32-macrocell device. This would give 2Hz resolution from a 32768Hz watch-crystal oscillator, but of course the jitter would be 30 microseconds which would probably be unacceptable for most applications. For lowest cost, probably the BCD rate multiplier is favourite. But it's very jittery. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●January 24, 20092009-01-24
Spoken (or written in this case) like an engineer: Great information, poor delivery. Thanks ... for the good info that is :-). "BobW" <nimby_GIMME_SOME_SPAM@roadrunner.com> wrote in message news:n9ydnU9yDP6Y7efUnZ2dnUVZ_hSWnZ2d@giganews.com...> > > > > "Rodo" <noway@youwish.com> wrote in message > news:Dvtel.1551$Aw2.414@nwrddc02.gnilink.net... >>I looked at the DDS info in the Altera site but I didn't see any mention >>that it was for the CPLDs. They talk about a megacore function and FPGAs. >>Can this be used in a MAX3000? >> >> I'm not doing anything fancy but cost and current consumption are an >> issue. I'd like to use as low a frequency I can to run the CPLD. Do you >> have any info on implementing a DDS? >> >> Thanks >> >> > > Do a web search for DDS. You'll find all the info you need. > > I used info from Google to design a DDS generator for a microcontroller. > You can do the same. If you can't then you should try a different career. > > Bob > -- > == All google group posts are automatically deleted due to spam == > > >
Reply by ●January 24, 20092009-01-24
On Jan 24, 11:41=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: -> For lowest cost, probably the BCD rate multiplier is -> favourite. =A0But it's very jittery. The jitter can be mitigated with a post-divider - eg at 1MHz you miss pulses giving edge uncertainties in the 1-2us region, at 10MHz that becomes 100-200ns Depends on what the final application is, and what low power really means. Building an Oscillator with lower power than the CPLD, is likely to be a challenge. The post divider can include a Sine DAC if the OP wishes. -jg
