Why the second flip-flop in Virtex-6?

"Nathan Bialke":

> In case anyone hasn't already seen, Xilinx has some preliminary
> information about Virtex-6 and Spartan-6 online here -
> http://www.xilinx.com/products/v6s6.htm .


Ok, and what's the real difference between virtex6 and spartan6?
The availability of TBUFs, again?

What I don't get with spartan3 is why they didn't put
some MUX logic into the switch matrices. I hate spending
much logic (and specially logic-levels!) on really nothing 
but a bus.

Gruss

Jan Bruns

On 3 f=E9v, 08:36, "Jan Bruns" <testzugang_janbr...@arcor.de> wrote:
> "Nathan Bialke":
>
> > In case anyone hasn't already seen, Xilinx has some preliminary
> > information about Virtex-6 and Spartan-6 online here -
> >http://www.xilinx.com/products/v6s6.htm.
>
> Ok, and what's the real difference between virtex6 and spartan6?
> The availability of TBUFs, again?
>
> What I don't get with spartan3 is why they didn't put
> some MUX logic into the switch matrices. I hate spending
> much logic (and specially logic-levels!) on really nothing
> but a bus.
>
> Gruss
>
> Jan Bruns

- Virtex 6 has a different DSP Block (DSP48E), with a 25x18 multiplier
instead of a 18x18 multiplier as in the Spartan-6 (DSP48A)
- Faster transceivers in Virtex-6
- 36kbit blockram (V6) instead of 18 kbit block ram (S6)
- System monitor in Virtex-6

And I suppose that the Virtex-6 will eventually come with PowerPcs
embedded in them and also they're probably much faster than Spartan-6.

I'm surprised that the Spartan-6 integrated memory controller does not support
DIMMs.  Also surprised that there are no integrated memory controllers in
Virtex-6.

Note the Virtex-6 Select-IO voltage range: only up to 2.5V!  2.5V is the
new 5V...


-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

On 3 f=E9v, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
> I'm surprised that the Spartan-6 integrated memory controller does not su=
pport
> DIMMs. =A0Also surprised that there are no integrated memory controllers =
in
> Virtex-6.
>
> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! =A02.5V is th=
e
> new 5V...

3.3V is the new 5V you might say

>
> --
> /* =A0jhal...@world.std.com AB1GO */ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0/* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=3D80;q+p-80;p-=3D2*a[p])for(z=3D9;z--;)q=
=3D3&(r=3Dtime(0)
> +r*57)/7,q=3Dq?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?=
!a[p+q*2
> ]?a[p+=3Da[p+=3Dq]=3Dq]=3Dq:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," =
#"[!a[q-1]]);}

In article <d41631f3-74f4-4d1a-b7e3-c601a24cc6da@v39g2000pro.googlegroups.com>,
Benjamin Couillard  <benjamin.couillard@gmail.com> wrote:
>On 3 f&#4294967295;v, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
>> I'm surprised that the Spartan-6 integrated memory controller does not support
>> DIMMs. &#4294967295;Also surprised that there are no integrated memory controllers in
>> Virtex-6.
>>
>> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! &#4294967295;2.5V is the
>> new 5V...
>
>3.3V is the new 5V you might say

No, 3.3V was the old new 5V.  The new new 5V is 2.5V.  Altera Straitx-IV
also does not support 3.3V I/O.

For recent designs I try to use 1.8V for I/O... there are a number of logic,
clock and peripheral chips which will work at this level, which matches DDR2
RAM power supply.

Not much available for 1.5V yet (for DDR3).

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

"Joseph H Allen":
> Benjamin Couillard  <benjamin.couillard@gmail.com> wrote:
>>On 3 f&#4294967295;v, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
>>> I'm surprised that the Spartan-6 integrated memory controller does not support
>>> DIMMs. Also surprised that there are no integrated memory controllers in
>>> Virtex-6.
>>>
>>> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! 2.5V is the
>>> new 5V...
>>
>>3.3V is the new 5V you might say

> No, 3.3V was the old new 5V.  The new new 5V is 2.5V.  Altera Straitx-IV
> also does not support 3.3V I/O.

Hm, ok, the old 5V-TTL logic devices pobably weren't compatible with
tube-level logic.

Gruss

Jan Bruns

"Benjamin Couillard":
> On 3 f&#4294967295;v, 08:36, "Jan Bruns" <testzugang_janbr...@arcor.de> wrote:

>> Ok, and what's the real difference between virtex6 and spartan6?
>> The availability of TBUFs, again?

>> What I don't get with spartan3 is why they didn't put
>> some MUX logic into the switch matrices. I hate spending
>> much logic (and specially logic-levels!) on really nothing
>> but a bus.

> - Virtex 6 has a different DSP Block (DSP48E), with a 25x18 multiplier
>   instead of a 18x18 multiplier as in the Spartan-6 (DSP48A)
> - Faster transceivers in Virtex-6
> - 36kbit blockram (V6) instead of 18 kbit block ram (S6)
> - System monitor in Virtex-6

> And I suppose that the Virtex-6 will eventually come with PowerPcs
> embedded in them and also they're probably much faster than Spartan-6.

Thanks, but that's not exactly what I meant to ask.
Will that Spartan6 have internal tristatable interconnects,
and/or better capabilites to build large MUXes?

In Spartan3, a usual way to make a 32:1 MUX requires 16 LUT4
(8 Slices, 2 CLBs) + F5MUX + 3 levels of FXMUXes and because
both CLBs won't absorb much of any logic following the mux32,
the result has to be routed far away.

It seems obvious to me that giving the spartan3 CLB additional full mux32
logic wasn't a theoretical problem nor would it blow up required routing
resources (since a CLB already has enough external interconnects), and
the remaining logic would still be theoretically usable without any
external routing blow up (maybe non-registered adders or registered
counters; not sure if these would mean exactly no blowup, but nearly).

Gruss

Jan Bruns

On Tue, 3 Feb 2009 22:25:48 +0100
"Jan Bruns" <testzugang_janbruns@arcor.de> wrote:

>=20
> "Benjamin Couillard":
> > On 3 f=E9v, 08:36, "Jan Bruns" <testzugang_janbr...@arcor.de> wrote:
>=20
> >> Ok, and what's the real difference between virtex6 and spartan6?
> >> The availability of TBUFs, again?
>=20
> >> What I don't get with spartan3 is why they didn't put
> >> some MUX logic into the switch matrices. I hate spending
> >> much logic (and specially logic-levels!) on really nothing
> >> but a bus.
>=20
> > - Virtex 6 has a different DSP Block (DSP48E), with a 25x18
> > multiplier instead of a 18x18 multiplier as in the Spartan-6
> > (DSP48A)
> > - Faster transceivers in Virtex-6
> > - 36kbit blockram (V6) instead of 18 kbit block ram (S6)
> > - System monitor in Virtex-6
>=20
> > And I suppose that the Virtex-6 will eventually come with PowerPcs
> > embedded in them and also they're probably much faster than
> > Spartan-6.
>=20
> Thanks, but that's not exactly what I meant to ask.
> Will that Spartan6 have internal tristatable interconnects,
> and/or better capabilites to build large MUXes?
>=20
> In Spartan3, a usual way to make a 32:1 MUX requires 16 LUT4
> (8 Slices, 2 CLBs) + F5MUX + 3 levels of FXMUXes and because
> both CLBs won't absorb much of any logic following the mux32,
> the result has to be routed far away.
>=20
> It seems obvious to me that giving the spartan3 CLB additional full
> mux32 logic wasn't a theoretical problem nor would it blow up
> required routing resources (since a CLB already has enough external
> interconnects), and the remaining logic would still be theoretically
> usable without any external routing blow up (maybe non-registered
> adders or registered counters; not sure if these would mean exactly
> no blowup, but nearly).
>=20
> Gruss
>=20
> Jan Bruns
>=20

I'm guessing that wide multiplexing was one of the major things driving
the move from LUT4s to LUT6s in the V5/V6/S6.  A LUT4 can only implement
a 2:1 +en mux, whereas the LUT6 means that your basic element can be a
4:1. So unless they've dumbed down the FiMUX logic, that means you get
a 32:1 at the F7MUX in one CLB, and a max 64:1 mux at the F8 mux.

--=20
Rob Gaddi, Highland Technology
Email address is currently out of order

Jan Bruns <testzugang_janbruns@arcor.de> wrote:
 
> Thanks, but that's not exactly what I meant to ask.
> Will that Spartan6 have internal tristatable interconnects,

As far as I know, that will never happen again.  It is part
of the scaling laws for MOS circuits that as the circuitry
gets smaller the RC time constant of wires increases.  
R increases faster than C decreases, resulting in slower
circuits.  The fix is to add buffers on longer lines,
but those are directional.

> and/or better capabilites to build large MUXes?

This should be possible.  As far as I know, AND/OR logic,
where the signal and its enable drive an AND gate, then
all the AND outputs drive an OR gate to generate the
result.  That can be distributed back to where it is needed.
 
> In Spartan3, a usual way to make a 32:1 MUX requires 16 LUT4
> (8 Slices, 2 CLBs) + F5MUX + 3 levels of FXMUXes and because
> both CLBs won't absorb much of any logic following the mux32,
> the result has to be routed far away.

Can you replace that with AND/OR logic?  

> It seems obvious to me that giving the spartan3 CLB additional full mux32
> logic wasn't a theoretical problem nor would it blow up required routing
> resources (since a CLB already has enough external interconnects), and
> the remaining logic would still be theoretically usable without any
> external routing blow up (maybe non-registered adders or registered
> counters; not sure if these would mean exactly no blowup, but nearly).

-- glen

Does anyone know that the V6 with a hard-core PowerPC is on the
roadmap?

Also, what about rad effects/atmospheric neutrons/SEE?  I wonder if
they've stuck this in a neutron beam yet.  (I work in avionics so this
actually is a concern, but from where devices are trending pretty soon
it'll be everyones problem).