pulser problem

Does anyone know how I can generate a pulser of maximum repition rate
of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
this signal before I use the actual pulser into the board

On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore238@gmail.com
wrote:

>Does anyone know how I can generate a pulser of maximum repition rate
>of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
>this signal before I use the actual pulser into the board

I think you want a clock source. Here is one way you can generate it:

`timescale 1ns/100fs
reg clk;
initial
begin
	pck = 0;
	forever clk = #10 ~clk;
end

This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and
you can change the number 10 to your needs.
Please note that this is only for testbench usage and you can't
actually put this in your fpga. You have to use an oscillator on your
board to generate a similar clock to drive into your fpga.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

On Feb 9, 1:36=A0am, Muzaffer Kal <k...@dspia.com> wrote:
> On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> wrote:
>
> >Does anyone know how I can generate a pulser of maximum repition rate
> >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
> >this signal before I use the actual pulser into the board
>
> I think you want a clock source. Here is one way you can generate it:
>
> `timescale 1ns/100fs
> reg clk;
> initial
> begin
> =A0 =A0 =A0 =A0 pck =3D 0;
> =A0 =A0 =A0 =A0 forever clk =3D #10 ~clk;
> end
>
> This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and
> you can change the number 10 to your needs.
> Please note that this is only for testbench usage and you can't
> actually put this in your fpga. You have to use an oscillator on your
> board to generate a similar clock to drive into your fpga.
>
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com

Hi,

I was did make myself clear. I would like to have a variable pulesr,
maximum 50 Mhz.

Thanks

On Feb 9, 6:09=A0pm, uraniumore...@gmail.com wrote:
> On Feb 9, 1:36=A0am, Muzaffer Kal <k...@dspia.com> wrote:
>
>
>
> > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> > wrote:
>
> > >Does anyone know how I can generate a pulser of maximum repition rate
> > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
> > >this signal before I use the actual pulser into the board
>
> > I think you want a clock source. Here is one way you can generate it:
>
> > `timescale 1ns/100fs
> > reg clk;
> > initial
> > begin
> > =A0 =A0 =A0 =A0 pck =3D 0;
> > =A0 =A0 =A0 =A0 forever clk =3D #10 ~clk;
> > end
>
> > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and
> > you can change the number 10 to your needs.
> > Please note that this is only for testbench usage and you can't
> > actually put this in your fpga. You have to use an oscillator on your
> > board to generate a similar clock to drive into your fpga.
>
> > Muzaffer Kal
>
> > DSPIA INC.
> > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> Hi,
>
> I was did make myself clear. I would like to have a variable pulesr,
> maximum 50 Mhz.
>
> Thanks

I think you made something very clear.

Antti

On Feb 9, 9:03=A0am, Antti <Antti.Luk...@googlemail.com> wrote:
> On Feb 9, 6:09=A0pm, uraniumore...@gmail.com wrote:
>
>
>
>
>
> > On Feb 9, 1:36=A0am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> > > wrote:
>
> > > >Does anyone know how I can generate a pulser of maximum repition rat=
e
> > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simula=
te
> > > >this signal before I use the actual pulser into the board
>
> > > I think you want a clock source. Here is one way you can generate it:
>
> > > `timescale 1ns/100fs
> > > reg clk;
> > > initial
> > > begin
> > > =A0 =A0 =A0 =A0 pck =3D 0;
> > > =A0 =A0 =A0 =A0 forever clk =3D #10 ~clk;
> > > end
>
> > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) an=
d
> > > you can change the number 10 to your needs.
> > > Please note that this is only for testbench usage and you can't
> > > actually put this in your fpga. You have to use an oscillator on your
> > > board to generate a similar clock to drive into your fpga.
>
> > > Muzaffer Kal
>
> > > DSPIA INC.
> > > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> > Hi,
>
> > I was did make myself clear. I would like to have a variable pulesr,
> > maximum 50 Mhz.
>
> > Thanks
>
> I think you made something very clear.
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Okay, I made a grammatical blunder there! All jokes aside...I wanted
to know if there is some code out there that would generate a variable
pulse of max 50Mhz...

thanks again,

On Feb 10, 2:07=A0pm, uraniumore...@gmail.com wrote:
> On Feb 9, 9:03=A0am, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On Feb 9, 6:09=A0pm, uraniumore...@gmail.com wrote:
>
> > > On Feb 9, 1:36=A0am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> > > > wrote:
>
> > > > >Does anyone know how I can generate a pulser of maximum repition r=
ate
> > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simu=
late
> > > > >this signal before I use the actual pulser into the board
>
> > > > I think you want a clock source. Here is one way you can generate i=
t:
>
> > > > `timescale 1ns/100fs
> > > > reg clk;
> > > > initial
> > > > begin
> > > > =A0 =A0 =A0 =A0 pck =3D 0;
> > > > =A0 =A0 =A0 =A0 forever clk =3D #10 ~clk;
> > > > end
>
> > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) =
and
> > > > you can change the number 10 to your needs.
> > > > Please note that this is only for testbench usage and you can't
> > > > actually put this in your fpga. You have to use an oscillator on yo=
ur
> > > > board to generate a similar clock to drive into your fpga.
>
> > > > Muzaffer Kal
>
> > > > DSPIA INC.
> > > > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> > > Hi,
>
> > > I was did make myself clear. I would like to have a variable pulesr,
> > > maximum 50 Mhz.
>
> > > Thanks
>
> > I think you made something very clear.
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -
>
> Okay, I made a grammatical blunder there! All jokes aside...I wanted
> to know if there is some code out there that would generate a variable
> pulse of max 50Mhz...
>
> thanks again,

You need to supply more info about your "variable pulse", such as
pulse width, duty cycle, and frequency.   So for the high end (as
someone else suggested) it sounds like you want 50MHz with 50% duty
cycle (10ns HI / 10ns LO).
-Dave Pollum

On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote:
> On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote:
>
>
>
> > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote:
>
> > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> > > > > wrote:
>
> > > > > >Does anyone know how I can generate a pulser of maximum repition rate
> > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
> > > > > >this signal before I use the actual pulser into the board
>
> > > > > I think you want a clock source. Here is one way you can generate it:
>
> > > > > `timescale 1ns/100fs
> > > > > reg clk;
> > > > > initial
> > > > > begin
> > > > >         pck = 0;
> > > > >         forever clk = #10 ~clk;
> > > > > end
>
> > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and
> > > > > you can change the number 10 to your needs.
> > > > > Please note that this is only for testbench usage and you can't
> > > > > actually put this in your fpga. You have to use an oscillator on your
> > > > > board to generate a similar clock to drive into your fpga.
>
> > > > > Muzaffer Kal
>
> > > > > DSPIA INC.
> > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> > > > Hi,
>
> > > > I was did make myself clear. I would like to have a variable pulesr,
> > > > maximum 50 Mhz.
>
> > > > Thanks
>
> > > I think you made something very clear.
>
> > > Antti- Hide quoted text -
>
> > > - Show quoted text -
>
> > Okay, I made a grammatical blunder there! All jokes aside...I wanted
> > to know if there is some code out there that would generate a variable
> > pulse of max 50Mhz...
>
> > thanks again,
>
> You need to supply more info about your "variable pulse", such as
> pulse width, duty cycle, and frequency.   So for the high end (as
> someone else suggested) it sounds like you want 50MHz with 50% duty
> cycle (10ns HI / 10ns LO).
> -Dave Pollum

The specs are:

minimum output pulse width: 10ns
Pulse Pair Resolution: 20ns
Maximum Repetition Rate (Periodic) 50MHz

On Feb 10, 2:58 pm, uraniumore...@gmail.com wrote:
> On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote:
>
>
>
> > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote:
>
> > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote:
>
> > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> > > > > > wrote:
>
> > > > > > >Does anyone know how I can generate a pulser of maximum repition rate
> > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
> > > > > > >this signal before I use the actual pulser into the board
>
> > > > > > I think you want a clock source. Here is one way you can generate it:
>
> > > > > > `timescale 1ns/100fs
> > > > > > reg clk;
> > > > > > initial
> > > > > > begin
> > > > > >         pck = 0;
> > > > > >         forever clk = #10 ~clk;
> > > > > > end
>
> > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and
> > > > > > you can change the number 10 to your needs.
> > > > > > Please note that this is only for testbench usage and you can't
> > > > > > actually put this in your fpga. You have to use an oscillator on your
> > > > > > board to generate a similar clock to drive into your fpga.
>
> > > > > > Muzaffer Kal
>
> > > > > > DSPIA INC.
> > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> > > > > Hi,
>
> > > > > I was did make myself clear. I would like to have a variable pulesr,
> > > > > maximum 50 Mhz.
>
> > > > > Thanks
>
> > > > I think you made something very clear.
>
> > > > Antti- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > Okay, I made a grammatical blunder there! All jokes aside...I wanted
> > > to know if there is some code out there that would generate a variable
> > > pulse of max 50Mhz...
>
> > > thanks again,
>
> > You need to supply more info about your "variable pulse", such as
> > pulse width, duty cycle, and frequency.   So for the high end (as
> > someone else suggested) it sounds like you want 50MHz with 50% duty
> > cycle (10ns HI / 10ns LO).
> > -Dave Pollum
>
> The specs are:
>
> minimum output pulse width: 10ns
> Pulse Pair Resolution: 20ns
> Maximum Repetition Rate (Periodic) 50MHz

Basically, this isn't a constant clock signal .. the repetition varies
over time. I am trying to mimic something like the following :
http://www.aricorp.com/combo100.htm

Thanks,

On Feb 10, 6:07=A0pm, uraniumore...@gmail.com wrote:
> On Feb 10, 2:58 pm, uraniumore...@gmail.com wrote:
>
>
>
> > On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote:
>
> > > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote:
>
> > > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote:
>
> > > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.=
com
> > > > > > > wrote:
>
> > > > > > > >Does anyone know how I can generate a pulser of maximum repi=
tion rate
> > > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like t=
o simulate
> > > > > > > >this signal before I use the actual pulser into the board
>
> > > > > > > I think you want a clock source. Here is one way you can gene=
rate it:
>
> > > > > > > `timescale 1ns/100fs
> > > > > > > reg clk;
> > > > > > > initial
> > > > > > > begin
> > > > > > > =A0 =A0 =A0 =A0 pck =3D 0;
> > > > > > > =A0 =A0 =A0 =A0 forever clk =3D #10 ~clk;
> > > > > > > end
>
> > > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns=
 low) and
> > > > > > > you can change the number 10 to your needs.
> > > > > > > Please note that this is only for testbench usage and you can=
't
> > > > > > > actually put this in your fpga. You have to use an oscillator=
 on your
> > > > > > > board to generate a similar clock to drive into your fpga.
>
> > > > > > > Muzaffer Kal
>
> > > > > > > DSPIA INC.
> > > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> > > > > > Hi,
>
> > > > > > I was did make myself clear. I would like to have a variable pu=
lesr,
> > > > > > maximum 50 Mhz.
>
> > > > > > Thanks
>
> > > > > I think you made something very clear.
>
> > > > > Antti- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > Okay, I made a grammatical blunder there! All jokes aside...I wante=
d
> > > > to know if there is some code out there that would generate a varia=
ble
> > > > pulse of max 50Mhz...
>
> > > > thanks again,
>
> > > You need to supply more info about your "variable pulse", such as
> > > pulse width, duty cycle, and frequency. =A0 So for the high end (as
> > > someone else suggested) it sounds like you want 50MHz with 50% duty
> > > cycle (10ns HI / 10ns LO).
> > > -Dave Pollum
>
> > The specs are:
>
> > minimum output pulse width: 10ns
> > Pulse Pair Resolution: 20ns
> > Maximum Repetition Rate (Periodic) 50MHz
>
> Basically, this isn't a constant clock signal .. the repetition varies
> over time. I am trying to mimic something like the following :http://www.=
aricorp.com/combo100.htm
>
> Thanks,

I'm still confused.  Are you trying to design hardware that
mimics the pulse generator, i.e. you want code you will
synthesize and program into the FPGA?

Or do you mean you want a test bench that mimics the
pulse generator to stimulate some other design during
simulation?

The two approaches would be very different.

regards,
Gabor

On Feb 10, 3:13 pm, Gabor <ga...@alacron.com> wrote:
> On Feb 10, 6:07 pm, uraniumore...@gmail.com wrote:
>
>
>
> > On Feb 10, 2:58 pm, uraniumore...@gmail.com wrote:
>
> > > On Feb 10, 1:07 pm, Dave Pollum <vze24...@verizon.net> wrote:
>
> > > > On Feb 10, 2:07 pm, uraniumore...@gmail.com wrote:
>
> > > > > On Feb 9, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > On Feb 9, 6:09 pm, uraniumore...@gmail.com wrote:
>
> > > > > > > On Feb 9, 1:36 am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > > > > > On Mon, 9 Feb 2009 01:18:21 -0800 (PST), uraniumore...@gmail.com
> > > > > > > > wrote:
>
> > > > > > > > >Does anyone know how I can generate a pulser of maximum repition rate
> > > > > > > > >of 50 Mhz in verilog .. into my existing design ? I'd like to simulate
> > > > > > > > >this signal before I use the actual pulser into the board
>
> > > > > > > > I think you want a clock source. Here is one way you can generate it:
>
> > > > > > > > `timescale 1ns/100fs
> > > > > > > > reg clk;
> > > > > > > > initial
> > > > > > > > begin
> > > > > > > >         pck = 0;
> > > > > > > >         forever clk = #10 ~clk;
> > > > > > > > end
>
> > > > > > > > This clock toggles at 50 MHz as you want (ie 10ns high, 10 ns low) and
> > > > > > > > you can change the number 10 to your needs.
> > > > > > > > Please note that this is only for testbench usage and you can't
> > > > > > > > actually put this in your fpga. You have to use an oscillator on your
> > > > > > > > board to generate a similar clock to drive into your fpga.
>
> > > > > > > > Muzaffer Kal
>
> > > > > > > > DSPIA INC.
> > > > > > > > ASIC/FPGA Design Serviceshttp://www.dspia.com
>
> > > > > > > Hi,
>
> > > > > > > I was did make myself clear. I would like to have a variable pulesr,
> > > > > > > maximum 50 Mhz.
>
> > > > > > > Thanks
>
> > > > > > I think you made something very clear.
>
> > > > > > Antti- Hide quoted text -
>
> > > > > > - Show quoted text -
>
> > > > > Okay, I made a grammatical blunder there! All jokes aside...I wanted
> > > > > to know if there is some code out there that would generate a variable
> > > > > pulse of max 50Mhz...
>
> > > > > thanks again,
>
> > > > You need to supply more info about your "variable pulse", such as
> > > > pulse width, duty cycle, and frequency.   So for the high end (as
> > > > someone else suggested) it sounds like you want 50MHz with 50% duty
> > > > cycle (10ns HI / 10ns LO).
> > > > -Dave Pollum
>
> > > The specs are:
>
> > > minimum output pulse width: 10ns
> > > Pulse Pair Resolution: 20ns
> > > Maximum Repetition Rate (Periodic) 50MHz
>
> > Basically, this isn't a constant clock signal .. the repetition varies
> > over time. I am trying to mimic something like the following :http://www.aricorp.com/combo100.htm
>
> > Thanks,
>
> I'm still confused.  Are you trying to design hardware that
> mimics the pulse generator, i.e. you want code you will
> synthesize and program into the FPGA?
>
> Or do you mean you want a test bench that mimics the
> pulse generator to stimulate some other design during
> simulation?
>
> The two approaches would be very different.
>
> regards,
> Gabor

If you can provide both that'll be good ..