Hi everybody, When configuring my Virtex 5 with encrypted bitstream (CCLK rate is 100 MHz) the FPGA doesn't start up ! whereas it is not the case for unencrypted one . Why ??? I need to configure the FPGA as quickly as possible. Thanks.
Virtex 5 slave serial config
Started by ●February 16, 2009
Reply by ●February 16, 20092009-02-16
On Feb 16, 12:16=A0pm, dajjou <swissiyous...@gmail.com> wrote:> Hi everybody, > > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > 100 MHz) the FPGA doesn't start up ! > whereas it is not the case for unencrypted one . Why ??? > I need to configure the FPGA as quickly as possible. > > Thanks.you need to use parallel mode :( i think the 100mhz ecnrypted mode may not be supported, please check the datasheets Antti
Reply by ●February 16, 20092009-02-16
On Feb 16, 5:37=A0am, Antti <Antti.Luk...@googlemail.com> wrote:> On Feb 16, 12:16=A0pm, dajjou <swissiyous...@gmail.com> wrote: > > > Hi everybody, > > > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > > 100 MHz) the FPGA doesn't start up ! > > whereas it is not the case for unencrypted one . Why ??? > > I need to configure the FPGA as quickly as possible. > > > Thanks. > > you need to use parallel mode :( > i think the 100mhz ecnrypted mode may not be supported, please > check the datasheets > > AnttiI've run into other problems at 100 MHz for unencrypted bitstreams as well. When the DONE signal is allowed to float high, the startup state logic can sample it in the threshold region (yes the chip samples the pin unless you set "Internal Done Pipe") and lock up. I solved this using the internal done pipe, but another recommendation was to "Drive Done High". My external DONE pullup was 330 ohms as recommended, but at 100 MHz, this is not fast enough. Another approach to fix this might be to slow down CCLK at or near the end of the bitstream. Regards, Gabor
Reply by ●February 17, 20092009-02-17
Gabor <gabor@alacron.com> wrote in news:e0edd268-99d3-44de-b126- 90be9409870d@m15g2000vbp.googlegroups.com:> On Feb 16, 5:37�am, Antti <Antti.Luk...@googlemail.com> wrote: >> On Feb 16, 12:16�pm, dajjou <swissiyous...@gmail.com> wrote: >> >> > Hi everybody, >> >> > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is >> > 100 MHz) the FPGA doesn't start up ! >> > whereas it is not the case for unencrypted one . Why ??? >> > I need to configure the FPGA as quickly as possible. >> >> > Thanks. >> >> you need to use parallel mode :( >> i think the 100mhz ecnrypted mode may not be supported, please >> check the datasheets >> >> Antti > > I've run into other problems at 100 MHz for unencrypted bitstreams > as well. When the DONE signal is allowed to float high, the > startup state logic can sample it in the threshold region > (yes the chip samples the pin unless you set "Internal Done Pipe") > and lock up. I solved this using the internal done pipe, but > another recommendation was to "Drive Done High". My external > DONE pullup was 330 ohms as recommended, but at 100 MHz, this > is not fast enough. Another approach to fix this might be to > slow down CCLK at or near the end of the bitstream.The last time I looked into this (Virtex2?), the specification for maximum frequency with encryption wasn't specified in the datasheets. The figure was specified in some obscure app note, and was something like 10MHz, much lower than the frequency allowed without encryption. Things may have improved with more recent FPGA families though. Regards, Allan
Reply by ●February 18, 20092009-02-18
On 17 f=E9v, 15:16, Allan Herriman <allanherri...@hotmail.com> wrote:> Gabor <ga...@alacron.com> wrote in news:e0edd268-99d3-44de-b126- > 90be94098...@m15g2000vbp.googlegroups.com: > > > > > On Feb 16, 5:37 am, Antti <Antti.Luk...@googlemail.com> wrote: > >> On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: > > >> > Hi everybody, > > >> > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > >> > 100 MHz) the FPGA doesn't start up ! > >> > whereas it is not the case for unencrypted one . Why ??? > >> > I need to configure the FPGA as quickly as possible. > > >> > Thanks. > > >> you need to use parallel mode :( > >> i think the 100mhz ecnrypted mode may not be supported, please > >> check the datasheets > > >> Antti > > > I've run into other problems at 100 MHz for unencrypted bitstreams > > as well. When the DONE signal is allowed to float high, the > > startup state logic can sample it in the threshold region > > (yes the chip samples the pin unless you set "Internal Done Pipe") > > and lock up. I solved this using the internal done pipe, but > > another recommendation was to "Drive Done High". My external > > DONE pullup was 330 ohms as recommended, but at 100 MHz, this > > is not fast enough. Another approach to fix this might be to > > slow down CCLK at or near the end of the bitstream. > > The last time I looked into this (Virtex2?), the specification for > maximum frequency with encryption wasn't specified in the datasheets. > The figure was specified in some obscure app note, and was something like > 10MHz, much lower than the frequency allowed without encryption. > > Things may have improved with more recent FPGA families though. > > Regards, > AllanHi ! I guess that decryption is done at the same frequency as the config rate, isent it ?
Reply by ●February 18, 20092009-02-18
On 16 f=E9v, 11:37, Antti <Antti.Luk...@googlemail.com> wrote:> On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: > > > Hi everybody, > > > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > > 100 MHz) the FPGA doesn't start up ! > > whereas it is not the case for unencrypted one . Why ??? > > I need to configure the FPGA as quickly as possible. > > > Thanks. > > you need to use parallel mode :( > i think the 100mhz ecnrypted mode may not be supported, please > check the datasheets > > Anttihello Antii, For encryption I am limited to x8 parallel mode, whereas for unencrypted one I could use x16 and x32 bus. Why ? There is a compromise between security and rapidity .
Reply by ●February 18, 20092009-02-18
On Feb 18, 10:31=A0am, dajjou <swissiyous...@gmail.com> wrote:> On 16 f=E9v, 11:37, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: > > > > Hi everybody, > > > > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > > > 100 MHz) the FPGA doesn't start up ! > > > whereas it is not the case for unencrypted one . Why ??? > > > I need to configure the FPGA as quickly as possible. > > > > Thanks. > > > you need to use parallel mode :( > > i think the 100mhz ecnrypted mode may not be supported, please > > check the datasheets > > > Antti > > hello Antii, > > =A0For encryption I am limited to x8 parallel mode, whereas for > unencrypted one I could use x16 and x32 bus. Why ? There is a > compromise between security and rapidity .yes there is Antti
Reply by ●February 18, 20092009-02-18
dajjou <swissiyoussef@gmail.com> wrote in news:9d0ab964-2168-4eb5-a0ce-a52421b3b3f4@i38g2000yqd.googlegroups.com:> On 17 f�v, 15:16, Allan Herriman <allanherri...@hotmail.com> wrote: >> Gabor <ga...@alacron.com> wrote in news:e0edd268-99d3-44de-b126- >> 90be94098...@m15g2000vbp.googlegroups.com: >> >> >> >> > On Feb 16, 5:37 am, Antti <Antti.Luk...@googlemail.com> wrote: >> >> On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: >> >> >> > Hi everybody, >> >> >> > When configuring my Virtex 5 with encrypted bitstream (CCLK rate >> >> > is 100 MHz) the FPGA doesn't start up ! >> >> > whereas it is not the case for unencrypted one . Why ??? >> >> > I need to configure the FPGA as quickly as possible. >> >> >> > Thanks. >> >> >> you need to use parallel mode :( >> >> i think the 100mhz ecnrypted mode may not be supported, please >> >> check the datasheets >> >> >> Antti >> >> > I've run into other problems at 100 MHz for unencrypted bitstreams >> > as well. When the DONE signal is allowed to float high, the >> > startup state logic can sample it in the threshold region >> > (yes the chip samples the pin unless you set "Internal Done Pipe") >> > and lock up. I solved this using the internal done pipe, but >> > another recommendation was to "Drive Done High". My external >> > DONE pullup was 330 ohms as recommended, but at 100 MHz, this >> > is not fast enough. Another approach to fix this might be to >> > slow down CCLK at or near the end of the bitstream. >> >> The last time I looked into this (Virtex2?), the specification for >> maximum frequency with encryption wasn't specified in the datasheets. >> The figure was specified in some obscure app note, and was something >> like 10MHz, much lower than the frequency allowed without encryption. >> >> Things may have improved with more recent FPGA families though. >> >> Regards, >> Allan > > Hi ! > I guess that decryption is done at the same frequency as the config > rate, isent it ?Yes, it is fairly obvious that it will decrypt the frames as they come in. Allan
Reply by ●February 18, 20092009-02-18
Hi, Thank you all for your answers. When I make a diff between the encrypted bitstream and the unencrypted one I realize that the encrypted one contains 9 extra NOP WORDS just before CRC checking. Moreover, I noted that he needs exactly 7 Nop words to start up my design when using x8 parallel mode and this is true for all config rates. My conclusion is that the decryptor(AES in CBC mode) needs these 7x4 clocks to decrypt the last block of the encrypted data (128 bits). Am I right ?
Reply by ●February 19, 20092009-02-19
dajjou <swissiyoussef@gmail.com> wrote in news:00da3286-d674-43ae-baa0- 749c2b1605d9@x38g2000yqj.googlegroups.com:> Hi, > Thank you all for your answers. > > When I make a diff between the encrypted bitstream and the unencrypted > one I realize that the encrypted one contains 9 extra NOP WORDS just > before CRC checking. > Moreover, I noted that he needs exactly 7 Nop words to start up my > design when using x8 parallel mode and this is true for all config > rates. > My conclusion is that the decryptor(AES in CBC mode) needs these 7x4 > clocks to decrypt the last block of the encrypted data (128 bits). > Am I right ? >From this web page: http://en.wikipedia.org/wiki/Block_cipher_modes_of_operation "[in] CBC ... the message must be padded to a multiple of the cipher block size." The block size is 128 bits in this case. Regards, Allan
