Re: VHDL long elsif state machine

Beat me to the punch.  I also recommend reading this paper and his others. 
 Case statements in VHDL are automatically parallel and full anyway.


---Matthew Hicks


> Gabor
> 
>> If it were Verilog I would use a case statement and
>> add "// synthesis parallel-case" to remove the priority
>> logic.  Since this is a synthesis directive, it might
>> also work in VHDL?
> If your assumption was wrong, would you expect to
> get any warnings before implementing your chip?
> See Cliff's paper titled,
> "full_case parallel_case", the Evil Twins of Verilog Synthesis
> at:  http://www.sunburst-design.com/papers/
> 
> Cheers,
> Jim
> A bird in the hand may be worth two in the bush,
> but it sure makes it hard to type.

Brad,

Your post actually contains two distinct, yet related, questions:

Question 1: does an if-elsif-elsif...-else statement always implement
a priority encoder?
Not always. Good synthesis tools will try to evaluate if all branch
conditions are mutually exclusive. If they indeed are, the synthesis
tool will build parallel logic, identical to the logic built from a
VHDL case statement or a truly full Verilog case statement.
Here is an example for when good synthesis tools will produce parallel
logic from an if-elsif statement:
   if A="01" then
      Z <= I1;
  elsif A="10" then
      Z <= I2;
  else
      Z <= I3;
Indeed, it is obvious that there is no overlap between the conditions.

Now, here is an example where a priority encoder will be inferred.
(Note: A and B are primary inputs to the design) :
   if A="1" then
      Z <= I1;
  elsif B="1" then
      Z <= I2;
  else
      Z <= I3;
Indeed, since are primary inputs to the design, there is no
information that tells that A and B might be mutually exclusive.

Question 2: how can I build parallel logic when, by design, my
conditions are mutually exclusive?
One solution consists in grouping the conditions into a single vector,
and using "don't care" assignments to indicate that the vector is in
fact one-hot. In the above example, if A and B are mutually exclusive
(implying the else condition is useless), you could recode it as:
   COND <= A & B; -- VHDL concatenation
   case COND is
      when "01" =>
         Z <= I1;
      when "10" =>
         Z <= I2;
      when others =>
         Z <= "--"; -- VHDL don't care assignment
   end case;

Et voila!

Finally, to relate closely to your example:
 - A is "state(33) or state(34) or state(35) or state(36)"
 - B is "state(37)"

Hope that helps,

 - gael