Xilinx FIFO problem

Hi,

I'm using EDK 10.1 with SP3 and ISE 10.1  with SP3

I generated a FIFO in ISE to use it in an EDK design. It is a 64 bit
wide and 512 deep FIFO. The fifo is created and implemented as ngc.
The simulation show the behaviour as expected, but in the actual
implementation in the FPGA it looks like the FIFO is full of zeros
after reset. After all zeros are read out of the fifo normal behaviour
starts again.

I hope someone can help me with this.

Thanks
Sebastian

OK, meanwhile I solved it.
I didn't know that the fifo still accepts the write enable, even if
reset is high. This cause filling up the fifo with zeros during reset.

Sebastian


On 24 Feb., 12:59, sebs <sebastian.schuep...@googlemail.com> wrote:
> Hi,
>
> I'm using EDK 10.1 with SP3 and ISE 10.1 =A0with SP3
>
> I generated a FIFO in ISE to use it in an EDK design. It is a 64 bit
> wide and 512 deep FIFO. The fifo is created and implemented as ngc.
> The simulation show the behaviour as expected, but in the actual
> implementation in the FPGA it looks like the FIFO is full of zeros
> after reset. After all zeros are read out of the fifo normal behaviour
> starts again.
>
> I hope someone can help me with this.
>
> Thanks
> Sebastian