New person to CPLD programming

I hope that CPLDs are okay to talk about on this FPGA newsgroup.  I'm just
starting out with CPLDs, I've ordered some XC9536 chips and am trying to do
some simple test projects with Xilinx's ICE program.  And I am getting
frustrated with it.  I move a part, and it throws errors (and disconnects
wires from the parts i just moved, so all in all, very irritating)

I wish I could find a simple, yet free graphical CPLD development program,
since right now, I don't know enough about any HDL language (VHDL/Verilog
HDL) yet.

Any help would be most appreciated.  I already know that I can build my own
programming cable, that's no issue.  The entering of the code is what is
giving me issues.

On Sun, 1 Mar 2009 02:38:41 -0600, "dracosilv" <dracosilver@wi.rr.com>
wrote:

>I hope that CPLDs are okay to talk about on this FPGA newsgroup.  I'm just
>starting out with CPLDs, I've ordered some XC9536 chips and am trying to do
>some simple test projects with Xilinx's ICE program.  And I am getting
>frustrated with it.  I move a part, and it throws errors (and disconnects
>wires from the parts i just moved, so all in all, very irritating)

If you don't define which device pins are associated with what
functions, the fitter is free to move things around as it see fit (no
pun intended (really!)).

When you have decided on a mapping of pins to functions, you use a UCF
(user constraint file) to lock them in place.

All arbitrary mappings of pins to functions will not be possible, due to
limitations just what resources are available in a particular CPLD. A
reasonable approach is to first setup a UCF with only your timing
constraints, fit that, and see how well it matches up with what you want
for the physical layout, then modify as necessary.

Look under Help | CPLD Design | Constraints.

-- 
Rich Webb     Norfolk, VA

Rich Webb wrote:
> On Sun, 1 Mar 2009 02:38:41 -0600, "dracosilv" <dracosilver@wi.rr.com>
> wrote:
>
>> I hope that CPLDs are okay to talk about on this FPGA newsgroup.
>> I'm just starting out with CPLDs, I've ordered some XC9536 chips and
>> am trying to do some simple test projects with Xilinx's ICE program.
>> And I am getting frustrated with it.  I move a part, and it throws
>> errors (and disconnects wires from the parts i just moved, so all in
>> all, very irritating)
>
> If you don't define which device pins are associated with what
> functions, the fitter is free to move things around as it see fit (no
> pun intended (really!)).
>
> When you have decided on a mapping of pins to functions, you use a UCF
> (user constraint file) to lock them in place.
>
> All arbitrary mappings of pins to functions will not be possible, due
> to limitations just what resources are available in a particular
> CPLD. A reasonable approach is to first setup a UCF with only your
> timing constraints, fit that, and see how well it matches up with
> what you want for the physical layout, then modify as necessary.
>
> Look under Help | CPLD Design | Constraints.

I think that I might have not defined the word 'pins' properly in my case.
I'm referring to the diagram on screen (the graphical layout)  I move one of
those devices around, and the program breaks the connections that I have
made to the bits of logic (tristate buffers, and gates, etc).  That's what
my issue is.

On Mar 1, 8:42=A0pm, "dracosilv" <dracosil...@wi.rr.com> wrote:
> Rich Webb wrote:
> > On Sun, 1 Mar 2009 02:38:41 -0600, "dracosilv" <dracosil...@wi.rr.com>
> > wrote:
>
> >> I hope that CPLDs are okay to talk about on this FPGA newsgroup.
> >> I'm just starting out with CPLDs, I've ordered some XC9536 chips and
> >> am trying to do some simple test projects with Xilinx's ICE program.
> >> And I am getting frustrated with it. =A0I move a part, and it throws
> >> errors (and disconnects wires from the parts i just moved, so all in
> >> all, very irritating)
>
> > If you don't define which device pins are associated with what
> > functions, the fitter is free to move things around as it see fit (no
> > pun intended (really!)).
>
> > When you have decided on a mapping of pins to functions, you use a UCF
> > (user constraint file) to lock them in place.
>
> > All arbitrary mappings of pins to functions will not be possible, due
> > to limitations just what resources are available in a particular
> > CPLD. A reasonable approach is to first setup a UCF with only your
> > timing constraints, fit that, and see how well it matches up with
> > what you want for the physical layout, then modify as necessary.
>
> > Look under Help | CPLD Design | Constraints.
>
> I think that I might have not defined the word 'pins' properly in my case=
.
> I'm referring to the diagram on screen (the graphical layout) =A0I move o=
ne of
> those devices around, and the program breaks the connections that I have
> made to the bits of logic (tristate buffers, and gates, etc). =A0That's w=
hat
> my issue is.

ISE schematic is really not made to be used.

with some effort you can get something done with it
but it is really not meant to be a design entry method

Antti

Antti.Lukats@googlemail.com wrote:
> On Mar 1, 8:42 pm, "dracosilv" <dracosil...@wi.rr.com> wrote:
[SNIPPED BECAUSE OF STUPID AIOE NOT LETTING ME QUOTE LOTS OF LINES]
>>
>> I think that I might have not defined the word 'pins' properly in my
>> case. I'm referring to the diagram on screen (the graphical layout)
>> I move one of those devices around, and the program breaks the
>> connections that I have made to the bits of logic (tristate buffers,
>> and gates, etc). That's what my issue is.
>
> ISE schematic is really not made to be used.
>
> with some effort you can get something done with it
> but it is really not meant to be a design entry method
>
> Antti

Any good suggestion for a schematic editor that *CAN* be acutally used?

dracosilv wrote:

> Rich Webb wrote:
> 
>>On Sun, 1 Mar 2009 02:38:41 -0600, "dracosilv" <dracosilver@wi.rr.com>
>>wrote:
>>
>>
>>>I hope that CPLDs are okay to talk about on this FPGA newsgroup.
>>>I'm just starting out with CPLDs, I've ordered some XC9536 chips and
>>>am trying to do some simple test projects with Xilinx's ICE program.
>>>And I am getting frustrated with it.  I move a part, and it throws
>>>errors (and disconnects wires from the parts i just moved, so all in
>>>all, very irritating)
>>
>>If you don't define which device pins are associated with what
>>functions, the fitter is free to move things around as it see fit (no
>>pun intended (really!)).
>>
>>When you have decided on a mapping of pins to functions, you use a UCF
>>(user constraint file) to lock them in place.
>>
>>All arbitrary mappings of pins to functions will not be possible, due
>>to limitations just what resources are available in a particular
>>CPLD. A reasonable approach is to first setup a UCF with only your
>>timing constraints, fit that, and see how well it matches up with
>>what you want for the physical layout, then modify as necessary.
>>
>>Look under Help | CPLD Design | Constraints.
> 
> 
> I think that I might have not defined the word 'pins' properly in my case.
> I'm referring to the diagram on screen (the graphical layout)  I move one of
> those devices around, and the program breaks the connections that I have
> made to the bits of logic (tristate buffers, and gates, etc).  That's what
> my issue is.
> 
> 
The schematic editor has it good points and its bad points. First of
all, your problem is easy to take care of.  On the right hand side of
the screen, under the file list part, there is a choice under a
section labelled: "when you move an object" of either "keep the
connections to other objects" or "break the connections to other
objects."  That will fix this issue.  However, moving things in
the editor is not easy to do quickly and it is hard to keep neat
schematics as a project grows. It is particularly annoying when
you move something to another sheet. If you use paste, special,
then you can keep the pin names but they will be invisible so
you have to rename them to make them visible.

Most people here do not use schematics. Using VHDL or verilog
gives them the opportunity to come here and ask how to trick
the system into doing what they want.  Getting brams is always
fun. With schematics you miss most of that since, if you want
a bram, you just put one in.

dracosilv wrote:

> Antti.Lukats@googlemail.com wrote:
> 
>>On Mar 1, 8:42 pm, "dracosilv" <dracosil...@wi.rr.com> wrote:
> 
> [SNIPPED BECAUSE OF STUPID AIOE NOT LETTING ME QUOTE LOTS OF LINES]
> 
>>>I think that I might have not defined the word 'pins' properly in my
>>>case. I'm referring to the diagram on screen (the graphical layout)
>>>I move one of those devices around, and the program breaks the
>>>connections that I have made to the bits of logic (tristate buffers,
>>>and gates, etc). That's what my issue is.
>>
>>ISE schematic is really not made to be used.
>>
>>with some effort you can get something done with it
>>but it is really not meant to be a design entry method
>>
>>Antti
> 
> 
> Any good suggestion for a schematic editor that *CAN* be acutally used?
> 
> 
You will not get much other choice since there are not many
to begin with. The tide is going to software since very few
people know hardware anymore.

doug wrote:
> dracosilv wrote:
>>
>> I think that I might have not defined the word 'pins' properly in my
>> case. I'm referring to the diagram on screen (the graphical layout)
>> I move one of those devices around, and the program breaks the
>> connections that I have made to the bits of logic (tristate buffers,
>> and gates, etc).  That's what my issue is.
>>
>>
> The schematic editor has it good points and its bad points. First of
> all, your problem is easy to take care of.  On the right hand side of
> the screen, under the file list part, there is a choice under a
> section labelled: "when you move an object" of either "keep the
> connections to other objects" or "break the connections to other
> objects."  That will fix this issue.  However, moving things in
> the editor is not easy to do quickly and it is hard to keep neat
> schematics as a project grows. It is particularly annoying when
> you move something to another sheet. If you use paste, special,
> then you can keep the pin names but they will be invisible so
> you have to rename them to make them visible.
>
> Most people here do not use schematics. Using VHDL or verilog
> gives them the opportunity to come here and ask how to trick
> the system into doing what they want.  Getting brams is always
> fun. With schematics you miss most of that since, if you want
> a bram, you just put one in.

Forgive me, but what is a bram?  As i mentioned earlier, I'm new to the very
interesting field of CPLDs/FPGAs.

doug wrote:
> dracosilv wrote:
>> [SNIPPED BECAUSE OF STUPID AIOE NOT LETTING ME QUOTE LOTS OF LINES]
>>
>> Any good suggestion for a schematic editor that *CAN* be acutally
>> used?
>>
>>
> You will not get much other choice since there are not many
> to begin with. The tide is going to software since very few
> people know hardware anymore.

So I guess that I'm stuck using a HDL then?

Well that sucks.

dracosilv wrote:

> doug wrote:
> 
>>dracosilv wrote:
>>
>>>I think that I might have not defined the word 'pins' properly in my
>>>case. I'm referring to the diagram on screen (the graphical layout)
>>>I move one of those devices around, and the program breaks the
>>>connections that I have made to the bits of logic (tristate buffers,
>>>and gates, etc).  That's what my issue is.
>>>
>>>
>>
>>The schematic editor has it good points and its bad points. First of
>>all, your problem is easy to take care of.  On the right hand side of
>>the screen, under the file list part, there is a choice under a
>>section labelled: "when you move an object" of either "keep the
>>connections to other objects" or "break the connections to other
>>objects."  That will fix this issue.  However, moving things in
>>the editor is not easy to do quickly and it is hard to keep neat
>>schematics as a project grows. It is particularly annoying when
>>you move something to another sheet. If you use paste, special,
>>then you can keep the pin names but they will be invisible so
>>you have to rename them to make them visible.
>>
>>Most people here do not use schematics. Using VHDL or verilog
>>gives them the opportunity to come here and ask how to trick
>>the system into doing what they want.  Getting brams is always
>>fun. With schematics you miss most of that since, if you want
>>a bram, you just put one in.
> 
> 
> Forgive me, but what is a bram?  As i mentioned earlier, I'm new to the very
> interesting field of CPLDs/FPGAs.

A bram is a blockram.  That is a memory block that is available
in some Xilinx fpgas.  Not in cplds though.

> 
>