32x32 -> 64 multiplier in virtex-5

Hi,
I'm porting an ASIC design to virtex-5. In the design there is a
32x32->64 bit signed multiplier and I can't seem to do any better than
synthesis at this point (tried two different synthesis tools which
give the same results also). What would be the fastest way to do a
32x32 multiplier in Virtex-5? I'm trying to get it to run at 125 MHz
on a xc5vlx50-1. Area is no problem and I'm currently using 4 DSP48E
blocks. I haven't tried a fabric only implementation but I can't
imagine that being faster. Alas adding pipelining to the existing
design is out of the question.

-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

On Mar 3, 11:59=A0pm, Muzaffer Kal <k...@dspia.com> wrote:
> Hi,
> I'm porting an ASIC design to virtex-5. In the design there is a
> 32x32->64 bit signed multiplier and I can't seem to do any better than
> synthesis at this point (tried two different synthesis tools which
> give the same results also). What would be the fastest way to do a
> 32x32 multiplier in Virtex-5? I'm trying to get it to run at 125 MHz
> on a xc5vlx50-1. Area is no problem and I'm currently using 4 DSP48E
> blocks. I haven't tried a fabric only implementation but I can't
> imagine that being faster. Alas adding pipelining to the existing
> design is out of the question.
>
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com

Four 16x16 multiplies and then added give 64 bits.  Perhaps the
additions can be register balanced further down stream within existing
pipeline stages.

newman5382@yahoo.com wrote:

> On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote:

>>I'm porting an ASIC design to virtex-5. In the design there is a
>>32x32->64 bit signed multiplier and I can't seem to do any better than
>>synthesis at this point 
(snip)

> Four 16x16 multiplies and then added give 64 bits.  Perhaps the
> additions can be register balanced further down stream within existing
> pipeline stages.

Well, 16x16 unsigned multiply, 16x16 signed multiply, and two
16x16 unsigned times signed multiply.

That isn't hard using the Xilinx 18x18 signed multiply though.

The correction needed to convert between them isn't that hard,
and could be pipelined along with the additions of partial products,
if the wider multiply wasn't available.

-- glen

On Mar 4, 3:11=A0pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> newman5...@yahoo.com wrote:
> > On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote:
> >>I'm porting an ASIC design to virtex-5. In the design there is a
> >>32x32->64 bit signed multiplier and I can't seem to do any better than
> >>synthesis at this point
>
> (snip)
>
> > Four 16x16 multiplies and then added give 64 bits. =A0Perhaps the
> > additions can be register balanced further down stream within existing
> > pipeline stages.
>
> Well, 16x16 unsigned multiply, 16x16 signed multiply, and two
> 16x16 unsigned times signed multiply.
>
> That isn't hard using the Xilinx 18x18 signed multiply though.
>
> The correction needed to convert between them isn't that hard,
> and could be pipelined along with the additions of partial products,
> if the wider multiply wasn't available.
>
> -- glen

I forgot about the signed part after I posted.  Thx.

On Wed, 04 Mar 2009 13:11:25 -0700, Glen Herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

>newman5382@yahoo.com wrote:
>
>> On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote:
>
>>>I'm porting an ASIC design to virtex-5. In the design there is a
>>>32x32->64 bit signed multiplier and I can't seem to do any better than
>>>synthesis at this point 
>(snip)
>
>> Four 16x16 multiplies and then added give 64 bits.  Perhaps the
>> additions can be register balanced further down stream within existing
>> pipeline stages.
>
>Well, 16x16 unsigned multiply, 16x16 signed multiply, and two
>16x16 unsigned times signed multiply.
>
>That isn't hard using the Xilinx 18x18 signed multiply though.
>
>The correction needed to convert between them isn't that hard,
>and could be pipelined along with the additions of partial products,
>if the wider multiply wasn't available.

Which is what I and synthesis are doing at the moment. The problem is
that TDSPCKO_PCOUTA_M in the part I'm using is is 4.23ns already so I
need to find another way. As I have mentioned in my initial post,
changing the existing pipeline is not an option as it would trigger a
huge verification task. Luckily there seems to be a way by going to an
internally faster clock and adding the pipeline there without changing
the interface.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

On Mar 4, 3:26=A0pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Wed, 04 Mar 2009 13:11:25 -0700, Glen Herrmannsfeldt
>
>
>
>
>
> <g...@ugcs.caltech.edu> wrote:
> >newman5...@yahoo.com wrote:
>
> >> On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote:
>
> >>>I'm porting an ASIC design to virtex-5. In the design there is a
> >>>32x32->64 bit signed multiplier and I can't seem to do any better than
> >>>synthesis at this point
> >(snip)
>
> >> Four 16x16 multiplies and then added give 64 bits. =A0Perhaps the
> >> additions can be register balanced further down stream within existing
> >> pipeline stages.
>
> >Well, 16x16 unsigned multiply, 16x16 signed multiply, and two
> >16x16 unsigned times signed multiply.
>
> >That isn't hard using the Xilinx 18x18 signed multiply though.
>
> >The correction needed to convert between them isn't that hard,
> >and could be pipelined along with the additions of partial products,
> >if the wider multiply wasn't available.
>
> Which is what I and synthesis are doing at the moment. The problem is
> that TDSPCKO_PCOUTA_M in the part I'm using is is 4.23ns already so I
> need to find another way. As I have mentioned in my initial post,
> changing the existing pipeline is not an option as it would trigger a
> huge verification task. Luckily there seems to be a way by going to an
> internally faster clock and adding the pipeline there without changing
> the interface.
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com- Hide quoted text -
>
> - Show quoted text -

You actually did not say changing the pipeline was not an option, you
said adding a pipeline was not an option.  I don't really know what
you are up against.  That is why I said perhaps. Good luck!

Muzaffer Kal <kal@dspia.com> writes:
> What would be the fastest way to do a
> 32x32 multiplier in Virtex-5?

Using four of the 18x18 multipliers out of the DSP48 blocks.