if i think of it, it should be doable? but i do not recall any projects that would use such transmit method normal FPGA LVDS are fast enough that it would be possible just capacitive decoupling sure some encoding should be applied but that shouldnt also be a problem Antti
FPGA LVDS for AC-decoupled transmit over CAT-5 cable
Started by ●March 11, 2009
Reply by ●March 11, 20092009-03-11
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:64c04f8c-9f8e-4523-b592-5fa017181654@j39g2000yqn.googlegroups.com...> if i think of it, it should be doable? > > but i do not recall any projects that would use such transmit method > > normal FPGA LVDS are fast enough that it would be possible just > capacitive decoupling > sure some encoding should be applied but that shouldnt also be a > problem > > AnttiHi Antti, You should probably use Manchester encoding or CMI if you intend to AC couple. Long strings of ones or zeroes in NRZ could give you problems. Dunno how far you can send stuff without some pre-emphasis and receive compensation, depends on your bitrate. Cheers, Syms.
Reply by ●March 11, 20092009-03-11
>if i think of it, it should be doable? > >but i do not recall any projects that would use such transmit method > >normal FPGA LVDS are fast enough that it would be possible just >capacitive decoupling >sure some encoding should be applied but that shouldnt also be a >problem > >Antti >Hi Antti ! I have not worked with AC-coupled systems yet, but i have read about AC-coupled LVDS transmission in an Xilinx Appnote, take a look at www.xilinx.com/support/documentation/application_notes/xapp756.pdf kind regards, julian
Reply by ●March 11, 20092009-03-11
Antti wrote:> if i think of it, it should be doable? > > but i do not recall any projects that would use such transmit method > > normal FPGA LVDS are fast enough that it would be possible just > capacitive decoupling > sure some encoding should be applied but that shouldnt also be a > problem > > AnttiYes it is possible, no, it is not a good idea. Running cables through the world always get you transients. It is much better to put a hardened lvds driver onto external cables since they are easier to replace than fpgas. We have done this both ways.
Reply by ●March 11, 20092009-03-11
"doug" <xx@xx.com> wrote in message news:uL2dnXB7JbmqoiXUnZ2dnUVZ_qjinZ2d@posted.docknet...> > > Antti wrote: > >> if i think of it, it should be doable? >> >> but i do not recall any projects that would use such transmit method >> >> normal FPGA LVDS are fast enough that it would be possible just >> capacitive decoupling >> sure some encoding should be applied but that shouldnt also be a >> problem >> >> Antti > > Yes it is possible, no, it is not a good idea. Running cables > through the world always get you transients. It is much better > to put a hardened lvds driver onto external cables since they > are easier to replace than fpgas. We have done this both > ways.Doug, I strongly disagree. A few reversed biased PIN diodes, some TVS diodes, and judicious routing beats 'hardened lvds drivers' every time. On cost, reliability, performance, manufacturability and board space. I would like to take this opportunity revise my original post, and recommend 8B10B coding to get rid of DC bias problem. 8B10B is out of patent now... HTH., Syms.
Reply by ●March 12, 20092009-03-12
On Mar 12, 2:39=A0am, "Symon" <symon_bre...@hotmail.com> wrote:> "doug" <x...@xx.com> wrote in message > > news:uL2dnXB7JbmqoiXUnZ2dnUVZ_qjinZ2d@posted.docknet... > > > > > > > Antti wrote: > > >> if i think of it, it should be doable? > > >> but i do not recall any projects that would use such transmit method > > >> normal FPGA LVDS are fast enough that it would be possible just > >> capacitive decoupling > >> sure some encoding should be applied but that shouldnt also be a > >> problem > > >> Antti > > > Yes it is possible, no, it is not a good idea. Running cables > > through the world always get you transients. It is much better > > to put a hardened lvds driver onto external cables since they > > are easier to replace than fpgas. We have done this both > > ways. > > Doug, > I strongly disagree. A few reversed biased PIN diodes, some TVS diodes, a=nd> judicious routing beats 'hardened lvds drivers' every time. On cost, > reliability, performance, manufacturability and board space. > I would like to take this opportunity revise my original post, and recomm=end> 8B10B coding to get rid of DC bias problem. 8B10B is out of patent now... > HTH., Syms.Hi thanks for all the answers, i also think it should be doable without external drivers Xilinx MGTs are qualified for PCIe and SATA, so I assume they might be used for PCIe over cable and eSATA, and in such cases there would be same situation as using ac decoupled CAT5 with LVDS I/Os, transient protection is of course good thing for any external cabling! Antti
Reply by ●March 12, 20092009-03-12
On Thu, 12 Mar 2009 00:39:32 -0000, "Symon" <symon_brewer@hotmail.com> wrote:> >"doug" <xx@xx.com> wrote in message >news:uL2dnXB7JbmqoiXUnZ2dnUVZ_qjinZ2d@posted.docknet... >> >> >> Antti wrote: >> >>> if i think of it, it should be doable? >>> >>> but i do not recall any projects that would use such transmit method >>> >>> normal FPGA LVDS are fast enough that it would be possible just >>> capacitive decoupling >>> sure some encoding should be applied but that shouldnt also be a >>> problem >>> >>> Antti >> >> Yes it is possible, no, it is not a good idea. Running cables >> through the world always get you transients. It is much better >> to put a hardened lvds driver onto external cables since they >> are easier to replace than fpgas. We have done this both >> ways. > >Doug, >I strongly disagree. A few reversed biased PIN diodes, some TVS diodes, and >judicious routing beats 'hardened lvds drivers' every time. On cost, >reliability, performance, manufacturability and board space. >I would like to take this opportunity revise my original post, and recommend >8B10B coding to get rid of DC bias problem. 8B10B is out of patent now... >HTH., Syms.If the patent was ever valid. The BBC were using a form of 8B10B coding (not,AFAIK, the exact same form as was patented but one with a delightfully simple implementation) for digital video transmission in early 1982; somewhat ahead of the priority date on the most-often quoted patent (though there may be other patents) - Brian
Reply by ●March 12, 20092009-03-12
Symon wrote:> "doug" <xx@xx.com> wrote in message > news:uL2dnXB7JbmqoiXUnZ2dnUVZ_qjinZ2d@posted.docknet... > >> >>Antti wrote: >> >> >>>if i think of it, it should be doable? >>> >>>but i do not recall any projects that would use such transmit method >>> >>>normal FPGA LVDS are fast enough that it would be possible just >>>capacitive decoupling >>>sure some encoding should be applied but that shouldnt also be a >>>problem >>> >>>Antti >> >>Yes it is possible, no, it is not a good idea. Running cables >>through the world always get you transients. It is much better >>to put a hardened lvds driver onto external cables since they >>are easier to replace than fpgas. We have done this both >>ways. > > > Doug, > I strongly disagree. A few reversed biased PIN diodes, some TVS diodes, and > judicious routing beats 'hardened lvds drivers' every time. On cost, > reliability, performance, manufacturability and board space. > I would like to take this opportunity revise my original post, and recommend > 8B10B coding to get rid of DC bias problem. 8B10B is out of patent now... > HTH., Syms.It kind of depends on how long you want them to work. One good chip giving several reliable lines takes no more spaces than your set of protectors. It also depends on how hard it is to get to the circuit to fix it. If it is on your bench, that is easy. If it is thousands of miles away well inside other assemblies, that is another issue. I would prefer to err on the side of conservatism. But I am not in a situation where the last penny counts.> >
Reply by ●March 12, 20092009-03-12
On Mar 11, 3:35=A0am, Antti <Antti.Luk...@googlemail.com> wrote:> if i think of it, it should be doable? > > but i do not recall any projects that would use such transmit method > > normal FPGA LVDS are fast enough that it would be possible just > capacitive decoupling > sure some encoding should be applied but that shouldnt also be a > problem > > AnttiI'm curious why you're interested in capacitive coupling. And - if you're looking at distant devices with grounds that can be a few volts off from each other - what data rates are you targeting? I'm thinking it might be reasonable to use ethernet magnetics to get rid of the bias problem yet still keep your data rates reasonable. The Cat5 system I did in a Spartan3e was fed (eventually) by the same power supply so isolation wasn't an issue for me. I designed for 600 Mb/s per channel but scaled back to about 400 Mb/s in the final design. - John_H
Reply by ●March 12, 20092009-03-12
On Mar 12, 7:09=A0pm, newsgr...@johnhandwork.com wrote:> On Mar 11, 3:35=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > if i think of it, it should be doable? > > > but i do not recall any projects that would use such transmit method > > > normal FPGA LVDS are fast enough that it would be possible just > > capacitive decoupling > > sure some encoding should be applied but that shouldnt also be a > > problem > > > Antti > > I'm curious why you're interested in capacitive coupling. =A0And - if > you're looking at distant devices with grounds that can be a few volts > off from each other - what data rates are you targeting? =A0I'm thinking > it might be reasonable to use ethernet magnetics to get rid of the > bias problem yet still keep your data rates reasonable. =A0The Cat5 > system I did in a Spartan3e was fed (eventually) by the same power > supply so isolation wasn't an issue for me. =A0I designed for 600 Mb/s > per channel but scaled back to about 400 Mb/s in the final design. > > - John_Hcuriuos? was just thinking of extending SPI like comms using cheapest and ready made cabling so one pair in each direction only. was hoping to get 50mbit/s? eSata uses capacitive decoupling, so i do not see big issues for cap decoupled LVDS, but yes special IC maybe more robust. and.. i do not like any wires direct to FPGA or MCU either (going off board/cable), have seen a Atmel to bulk erase itself because the reset line was in 2 meter long cable parallel to wire carrying 12V (reed relay switched) (well Atmel claimed such bulk erase is impossible... but it happened twice and second time i had another guy to witness it, so i wasnt seeing ghosts) so i would normally design some buffer or at least current limiting resistor for any wires going off board Antti
