Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz

On Mar 11, 8:01=A0pm, Jacko <jackokr...@gmail.com> wrote:
> Hi
>
> > PS i have hard times understanding your nibz thing, sorry..
> > maybe my brain is not screwed enough to understand it ;)
>
> A minimal microprocessor for tight logic area constraints. A minimal
> microprocessor for such large component technologies like optical/
> photonic computing. A minimal microprocessor for developing 1000+ core
> SoC designs. A minimal microprocessor for super low power
> applications/ A minimal microprocessor for designing/executing highly
> portable and simple to bootstrap implement languages. In general then
> a minimal microprocessor.
>
> The BSD licence is open source yes, but it does not limit ME to only
> offering a BSD licence. Maybe there are people who do not wish to use
> the BSD licence, but would be happy with the above licence.
>
> cheers jacko

so how much stack you get into the maxII- 570?

i'm just curious

Antti

Antti.Lukats@googlemail.com wrote:
> On Mar 11, 8:01 pm, Jacko <jackokr...@gmail.com> wrote:
> 
>>Hi
>>
>>
>>>PS i have hard times understanding your nibz thing, sorry..
>>>maybe my brain is not screwed enough to understand it ;)

I too found the description hard to understand, which is a pity 
because there may be some interesting ideas hiding there.

>>A minimal microprocessor for tight logic area constraints. A minimal
>>microprocessor for such large component technologies like optical/
>>photonic computing. A minimal microprocessor for developing 1000+ core
>>SoC designs. A minimal microprocessor for super low power
>>applications/ A minimal microprocessor for designing/executing highly
>>portable and simple to bootstrap implement languages. In general then
>>a minimal microprocessor.

Yes, yes, it is clear that these are the goals. But what is the 
processor architecture? The description of the registers and 
instructions is very hard to understand. For example, you say that 
there is an instruction called "BA" and describe its "Details" as 
"BA (R)->P - Back". That is far from clear.

You seem to be using some kind of personal abbreviated notation and 
terminology, perhaps based on Forth (in which I am not fluent). If 
you want to attract users to this processor, make an effort to 
describe its architecture in common prose, and include some 
examples with explanations.

-- 
Niklas Holsti
Tidorum Ltd
niklas holsti tidorum fi
       .      @       .

On 11 Mar, 18:27, Niklas Holsti <niklas.hol...@tidorum.invalid> wrote:
> Antti.Luk...@googlemail.com wrote:
> > On Mar 11, 8:01 pm, Jacko <jackokr...@gmail.com> wrote:
>
> >>Hi
>
> >>>PS i have hard times understanding your nibz thing, sorry..
> >>>maybe my brain is not screwed enough to understand it ;)
>
> I too found the description hard to understand, which is a pity
> because there may be some interesting ideas hiding there.

ok.

> >>A minimal microprocessor for tight logic area constraints. A minimal
> >>microprocessor for such large component technologies like optical/
> >>photonic computing. A minimal microprocessor for developing 1000+ core
> >>SoC designs. A minimal microprocessor for super low power
> >>applications/ A minimal microprocessor for designing/executing highly
> >>portable and simple to bootstrap implement languages. In general then
> >>a minimal microprocessor.
>
> Yes, yes, it is clear that these are the goals. But what is the
> processor architecture? The description of the registers and
> instructions is very hard to understand. For example, you say that
> there is an instruction called "BA" and describe its "Details" as
> "BA (R)->P - Back". That is far from clear.

BA instruction is indirect memory via R register and place contents
into P register, i.e. pop return stack into program counter. (with
auto post increment as all indirect memory reads do on this
processor). The brackets are indirect memory access, the -> is
register transfer.

> You seem to be using some kind of personal abbreviated notation and
> terminology, perhaps based on Forth (in which I am not fluent). If
> you want to attract users to this processor, make an effort to
> describe its architecture in common prose, and include some
> examples with explanations.

I'll think about it, and maybe add it to wiki.

Cheers jacko

Hi
> so how much stack you get into the maxII- 570?

None. indirect memory access is used.

Cheers jacko

On Mar 11, 2:27 pm, Niklas Holsti <niklas.hol...@tidorum.invalid>
wrote:
> Antti.Luk...@googlemail.com wrote:
> > On Mar 11, 8:01 pm, Jacko <jackokr...@gmail.com> wrote:
>
> >>Hi
>
> >>>PS i have hard times understanding your nibz thing, sorry..
> >>>maybe my brain is not screwed enough to understand it ;)
>
> I too found the description hard to understand, which is a pity
> because there may be some interesting ideas hiding there.
>
> >>A minimal microprocessor for tight logic area constraints. A minimal
> >>microprocessor for such large component technologies like optical/
> >>photonic computing. A minimal microprocessor for developing 1000+ core
> >>SoC designs. A minimal microprocessor for super low power
> >>applications/ A minimal microprocessor for designing/executing highly
> >>portable and simple to bootstrap implement languages. In general then
> >>a minimal microprocessor.
>
> Yes, yes, it is clear that these are the goals. But what is the
> processor architecture? The description of the registers and
> instructions is very hard to understand. For example, you say that
> there is an instruction called "BA" and describe its "Details" as
> "BA (R)->P - Back". That is far from clear.
>
> You seem to be using some kind of personal abbreviated notation and
> terminology, perhaps based on Forth (in which I am not fluent). If
> you want to attract users to this processor, make an effort to
> describe its architecture in common prose, and include some
> examples with explanations.
>
> --
> Niklas Holsti
> Tidorum Ltd
> niklas holsti tidorum fi
>        .      @       .

I've tried to understand what this processor is about and I have never
been able to "get it".  As you indicate, the notation is very cryptic
as is a lot of what he says.  I remember a qwerty who used to post in
some of these groups who would make all sorts of claims, but never
seemed to have anything to offer.  jacko seems to be doing some
interesting work, but it is mostly not intelligible to us mere
mortals.

jacko, please don't take me wrong.  I don't mean to belittle you in
any way.  I'm just trying to make the point that if you don't
communicate well, you have little impact on the rest of the world.  If
that is ok with you, it doesn't matter to me.  I'm just making an
observation.

Enjoy,

Rick

On Mar 12, 2:24=A0am, Jacko <jackokr...@gmail.com> wrote:
> Hi
>
> > so how much stack you get into the maxII- 570?
>
> None. indirect memory access is used.
>
> Cheers jacko

Dear Creative technologist Simon jackson, BEng.

if nibz can not work from inside MAXII-570 (without external memory)
then it is absolutly no need to mention MAXII at all. If nibz needs
external ram, then it is is 200% sure nobody will ever use it in MAXII
570

hence the logic utilization comparison to MAXII-570 LE's is absolutly
meaningless and confusing...

MAXII is a bad FPGA, as Altera made design mistakes (no distributed
ram!)
so it is also bad idea to use reference to it for marketing. unless...

unless your processor could work with MAXII and not external
components!!

I do have a MAXII optimized processor design that fits <240 MAXII LE's
and is useable, but it was real hard design and compromise to get
it useable at all. Very small soft-cores are possible and useable as
example Actel CoreABC can be optimized by GUI settingsto very
very low logic utilization.

Using CoreABC to perform SD card init SD/SDHC for SD mode (not SPI)
yields to Actel utilization of about 640 Verstaliles. Versatiles are 3
input
logic, and much smaller than MAXII LE as they can not use FF in same
LE where logic is utilized.

this CoreABC config implements the ROM in logic made out of 3 input
LE's, and the example utilization is smaller than 570 if compared to
MAXII LE's. And the example is verified in real FPGA with real SD
card.

your SD card boot mentioned, have you ever tried it on real FPGA?
the CoreABC SD card init worked the VERY first time tested on
real FPGA with real SD. And it was programmed in assembler.
in Assembler for a architecture previously unknown to me.

you claim your forth to be somewhat portable, so one should
think it would be simple to get programs working right?

so why havent you to verified the SD card boot?

back to nibz-MAXII, if you talk about 1000's of cores to be used
then well they must run from internal block rams, and MAXII
doesnt have them, those you should provide some design
for other architectures, and examples how the nibz arrays work

about your licensing, sorry to be joy-killer but:
your total earnings from the paypal donation that you advertize on
your site will be about 42$ for the all product lifetime.
belive me, this number is highly accurate.

your "logo" request: no large scale company will ever consider
adding the current bad quality bitmap image of he Kring logo
to any ASIC or product PCB. Should it happen I will go buy a
hat just to be able to eat it.

jacko - I am not the bad guy, any feedback is good feedback,
really! Most people just dont care.

I am still looking for a good small soft-core, and well it seem
not to exist... it not nibz for sure. Even if the nibz arch it super
the doc and related tools are missing or cryptic, so nobody
would ever take the effort to really evaluate and understand
what you have done, it too much time needed.

Antti

On Mar 12, 1:34=A0am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
>
> MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> ram!)
> so it is also bad idea to use reference to it for marketing. unless...

Does Altera have *any* FPGAs with distributed ram?  I thought that
distributed ram (using the LUT ram as real ram) was patented by Xilinx
although Lattice has a license to use it (they got it when they bought
the Lucent ORCA line which Lucent licensed from Xilinx).  I think this
patent is still in force although it is likely reaching its end of
life in a very few years.

I think distributed ram is much less important now although I will say
it can come in handy.  I am looking at using it in a possible design,
not in place of the block ram, but because I don't have enough block
ram!  I need a sizable delay line and I need another 208 bytes of
delay.  So I'll use 104 LUTs in a serial chain along with two blocks
of ram.  That will leave 4 blocks for the on chip CPU.


> unless your processor could work with MAXII and not external
> components!!
>
> I do have a MAXII optimized processor design that fits <240 MAXII LE's
> and is useable, but it was real hard design and compromise to get
> it useable at all. Very small soft-cores are possible and useable as
> example Actel CoreABC can be optimized by GUI settingsto very
> very low logic utilization.

Is your CPU available to view?  I am always interested in a decent CPU
design for FPGAs.


> your SD card boot mentioned, have you ever tried it on real FPGA?
> the CoreABC SD card init worked the VERY first time tested on
> real FPGA with real SD. And it was programmed in assembler.
> in Assembler for a architecture previously unknown to me.

I am very interested in any code to access SD cards.  One idea I would
like to put into place is to put a
CPU in my test fixture FPGA which would read a bit stream from the SD
card and program the FPGA on the target board/UUT.  Then it would read
a second file which contains the test procedure and conduct the test
of the UUT.  I'm not certain that I can do this because I am sharing I/
O lines between the SD card and some RS-422 chips used to test the
UUT.  So the SD card would have to be removed and then plugged back in
for every card.  Still, I would be interested in your code, or even
just the info you used to understand how to read it.  I assume you are
using a file system and not just treating the SD as a flash memory.


> I am still looking for a good small soft-core, and well it seem
> not to exist...

I seem to recall that you were trying to find a bit serial CPU that
would be the smallest possible in an FPGA.  Did you ever find one you
liked?  Personally, I think that is a goal with a very low target
application size.  But certainly there are some apps where this could
be useful.

My potential app might will work with such a processor.  It will be
receiving 16 bit data at a 1 kHz rate which it will decode into a 200
bps bit stream with 2 bits per symbol at 100 Hz symbol rate (and/or
the other direction).  That is pretty low bandwidth.  A potential
future app would be the same algorithm at 10x the data rates.

My existing processor design was using around 600 LUTs in an Altera
ACEX 1K part.  I have not yet ported it to my new target, a Lattice XP
device (block ram, but no multipliers).  If I take out some of the
stuff intended for debugging, it might be as small as 400 LUTs, but I
can't be sure just yet.

Rick

On Mar 12, 8:57=A0pm, rickman <gnu...@gmail.com> wrote:
> I seem to recall that you were trying to find a bit serial CPU that
> would be the smallest possible in an FPGA. =A0Did you ever find one you
> liked? =A0Personally, I think that is a goal with a very low target
> application size. =A0But certainly there are some apps where this could
> be useful.

Bit-serial (like Cop8) only makes size-sense to simplify bus routing.
- but that's almost free in a FPGA, so other needs better drive Bit-
Serial.

Bit-serial Multiply/divide can save resource, but that's less a core
than
an algortihm  trade-off, and Mul/Div are rare in the smallest cores
anyway.

One plus that appeals to me, is Execute from Serial FLASH, (and now
Serial RAM)
[does a nibble fetch from 4 bit SPI still count as Bit-serial ? ]
 as resource space. Saves MANY pins, and PCB space, but I'm not sure
the
core will be _smaller_ as a result - more likely slightly larger ?

-jg

On 12 Mar, 05:34, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Mar 12, 2:24 am, Jacko <jackokr...@gmail.com> wrote:
>
> > Hi
>
> > > so how much stack you get into the maxII- 570?
>
> > None. indirect memory access is used.
>
> > Cheers jacko
>
> Dear Creative technologist Simon jackson, BEng.
>
> if nibz can not work from inside MAXII-570 (without external memory)
> then it is absolutly no need to mention MAXII at all. If nibz needs
> external ram, then it is is 200% sure nobody will ever use it in MAXII
> 570

If you remove the ports (40 programmable IO pins) the design will
shrink, and free some space for a very small RAM area.

> hence the logic utilization comparison to MAXII-570 LE's is absolutly
> meaningless and confusing...
>
> MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> ram!)
> so it is also bad idea to use reference to it for marketing. unless...

Marketting ?

> unless your processor could work with MAXII and not external
> components!!
>
> I do have a MAXII optimized processor design that fits <240 MAXII LE's
> and is useable, but it was real hard design and compromise to get
> it useable at all. Very small soft-cores are possible and useable as
> example Actel CoreABC can be optimized by GUI settingsto very
> very low logic utilization.
>
> Using CoreABC to perform SD card init SD/SDHC for SD mode (not SPI)
> yields to Actel utilization of about 640 Verstaliles. Versatiles are 3
> input
> logic, and much smaller than MAXII LE as they can not use FF in same
> LE where logic is utilized.
>
> this CoreABC config implements the ROM in logic made out of 3 input
> LE's, and the example utilization is smaller than 570 if compared to
> MAXII LE's. And the example is verified in real FPGA with real SD
> card.
>
> your SD card boot mentioned, have you ever tried it on real FPGA?
> the CoreABC SD card init worked the VERY first time tested on
> real FPGA with real SD. And it was programmed in assembler.
> in Assembler for a architecture previously unknown to me.

Sounds good.

> you claim your forth to be somewhat portable, so one should
> think it would be simple to get programs working right?

I do no t claim any thing of MY forth, it is a non complete gforth EC
port.

> so why havent you to verified the SD card boot?

For the same rason.

> back to nibz-MAXII, if you talk about 1000's of cores to be used
> then well they must run from internal block rams, and MAXII
> doesnt have them, those you should provide some design
> for other architectures, and examples how the nibz arrays work

Quarus II allows migration to Hard Copy II with 10 minuites.

> about your licensing, sorry to be joy-killer but:
> your total earnings from the paypal donation that you advertize on
> your site will be about 42$ for the all product lifetime.
> belive me, this number is highly accurate.

Probbably.

> your "logo" request: no large scale company will ever consider
> adding the current bad quality bitmap image of he Kring logo
> to any ASIC or product PCB. Should it happen I will go buy a
> hat just to be able to eat it.

A hat with an ARM logo perhaps ;-)

> jacko - I am not the bad guy, any feedback is good feedback,
> really! Most people just dont care.

ok.

> I am still looking for a good small soft-core, and well it seem
> not to exist... it not nibz for sure. Even if the nibz arch it super
> the doc and related tools are missing or cryptic, so nobody
> would ever take the effort to really evaluate and understand
> what you have done, it too much time needed.

Probably.

On 12 Mar, 07:57, rickman <gnu...@gmail.com> wrote:
> On Mar 12, 1:34 am, "Antti.Luk...@googlemail.com"
>
> <Antti.Luk...@googlemail.com> wrote:
>
> > MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> > ram!)
> > so it is also bad idea to use reference to it for marketing. unless...
>
> Does Altera have *any* FPGAs with distributed ram?  I thought that
> distributed ram (using the LUT ram as real ram) was patented by Xilinx
> although Lattice has a license to use it (they got it when they bought
> the Lucent ORCA line which Lucent licensed from Xilinx).  I think this
> patent is still in force although it is likely reaching its end of
> life in a very few years.

Cyclone -> Statix -> HardCopy.
M4K blocks other.

> I think distributed ram is much less important now although I will say
> it can come in handy.  I am looking at using it in a possible design,
> not in place of the block ram, but because I don't have enough block
> ram!  I need a sizable delay line and I need another 208 bytes of
> delay.  So I'll use 104 LUTs in a serial chain along with two blocks
> of ram.  That will leave 4 blocks for the on chip CPU.

ok.

> > unless your processor could work with MAXII and not external
> > components!!
>
> > I do have a MAXII optimized processor design that fits <240 MAXII LE's
> > and is useable, but it was real hard design and compromise to get
> > it useable at all. Very small soft-cores are possible and useable as
> > example Actel CoreABC can be optimized by GUI settingsto very
> > very low logic utilization.
>
> Is your CPU available to view?  I am always interested in a decent CPU
> design for FPGAs.
>
> > your SD card boot mentioned, have you ever tried it on real FPGA?
> > the CoreABC SD card init worked the VERY first time tested on
> > real FPGA with real SD. And it was programmed in assembler.
> > in Assembler for a architecture previously unknown to me.
>
> I am very interested in any code to access SD cards.  One idea I would
> like to put into place is to put a
> CPU in my test fixture FPGA which would read a bit stream from the SD
> card and program the FPGA on the target board/UUT.  Then it would read
> a second file which contains the test procedure and conduct the test
> of the UUT.  I'm not certain that I can do this because I am sharing I/
> O lines between the SD card and some RS-422 chips used to test the
> UUT.  So the SD card would have to be removed and then plugged back in
> for every card.  Still, I would be interested in your code, or even
> just the info you used to understand how to read it.  I assume you are
> using a file system and not just treating the SD as a flash memory.
>
> > I am still looking for a good small soft-core, and well it seem
> > not to exist...
>
> I seem to recall that you were trying to find a bit serial CPU that
> would be the smallest possible in an FPGA.  Did you ever find one you
> liked?  Personally, I think that is a goal with a very low target
> application size.  But certainly there are some apps where this could
> be useful.
>
> My potential app might will work with such a processor.  It will be
> receiving 16 bit data at a 1 kHz rate which it will decode into a 200
> bps bit stream with 2 bits per symbol at 100 Hz symbol rate (and/or
> the other direction).  That is pretty low bandwidth.  A potential
> future app would be the same algorithm at 10x the data rates.
>
> My existing processor design was using around 600 LUTs in an Altera
> ACEX 1K part.  I have not yet ported it to my new target, a Lattice XP
> device (block ram, but no multipliers).  If I take out some of the
> stuff intended for debugging, it might be as small as 400 LUTs, but I
> can't be sure just yet.
>
> Rick

cheers jacko