Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz

On Mar 12, 9:57=A0am, rickman <gnu...@gmail.com> wrote:
> On Mar 12, 1:34=A0am, "Antti.Luk...@googlemail.com"
>
> <Antti.Luk...@googlemail.com> wrote:
>
> > MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> > ram!)
> > so it is also bad idea to use reference to it for marketing. unless...
>
> Does Altera have *any* FPGAs with distributed ram? =A0I thought that
> distributed ram (using the LUT ram as real ram) was patented by Xilinx
> although Lattice has a license to use it (they got it when they bought
> the Lucent ORCA line which Lucent licensed from Xilinx). =A0I think this
> patent is still in force although it is likely reaching its end of
> life in a very few years.
>
> I think distributed ram is much less important now although I will say
> it can come in handy. =A0I am looking at using it in a possible design,
> not in place of the block ram, but because I don't have enough block
> ram! =A0I need a sizable delay line and I need another 208 bytes of
> delay. =A0So I'll use 104 LUTs in a serial chain along with two blocks
> of ram. =A0That will leave 4 blocks for the on chip CPU.
>
> > unless your processor could work with MAXII and not external
> > components!!
>
> > I do have a MAXII optimized processor design that fits <240 MAXII LE's
> > and is useable, but it was real hard design and compromise to get
> > it useable at all. Very small soft-cores are possible and useable as
> > example Actel CoreABC can be optimized by GUI settingsto very
> > very low logic utilization.
>
> Is your CPU available to view? =A0I am always interested in a decent CPU
> design for FPGAs.
>
> > your SD card boot mentioned, have you ever tried it on real FPGA?
> > the CoreABC SD card init worked the VERY first time tested on
> > real FPGA with real SD. And it was programmed in assembler.
> > in Assembler for a architecture previously unknown to me.
>
> I am very interested in any code to access SD cards. =A0One idea I would
> like to put into place is to put a
> CPU in my test fixture FPGA which would read a bit stream from the SD
> card and program the FPGA on the target board/UUT. =A0Then it would read
> a second file which contains the test procedure and conduct the test
> of the UUT. =A0I'm not certain that I can do this because I am sharing I/
> O lines between the SD card and some RS-422 chips used to test the
> UUT. =A0So the SD card would have to be removed and then plugged back in
> for every card. =A0Still, I would be interested in your code, or even
> just the info you used to understand how to read it. =A0I assume you are
> using a file system and not just treating the SD as a flash memory.
>
> > I am still looking for a good small soft-core, and well it seem
> > not to exist...
>
> I seem to recall that you were trying to find a bit serial CPU that
> would be the smallest possible in an FPGA. =A0Did you ever find one you
> liked? =A0Personally, I think that is a goal with a very low target
> application size. =A0But certainly there are some apps where this could
> be useful.
>
> My potential app might will work with such a processor. =A0It will be
> receiving 16 bit data at a 1 kHz rate which it will decode into a 200
> bps bit stream with 2 bits per symbol at 100 Hz symbol rate (and/or
> the other direction). =A0That is pretty low bandwidth. =A0A potential
> future app would be the same algorithm at 10x the data rates.
>
> My existing processor design was using around 600 LUTs in an Altera
> ACEX 1K part. =A0I have not yet ported it to my new target, a Lattice XP
> device (block ram, but no multipliers). =A0If I take out some of the
> stuff intended for debugging, it might be as small as 400 LUTs, but I
> can't be sure just yet.
>
> Rick

Hi Rick,

my CPU is available for view, if i find it again.. its on the search
path over 6 external HDD's

as of distributed RAM it looks the patent is hold by:

Altera Corporation, not Xilinx

http://www.freepatentsonline.com/5352940.html

but maybe i need sunglasses

and no, i havent found the dream CPU yet ;) as always need todo it
itself i guess

Antti

On 12 Mar, 15:09, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Mar 12, 9:57=A0am, rickman <gnu...@gmail.com> wrote:
>
>
>
>
>
> > On Mar 12, 1:34=A0am, "Antti.Luk...@googlemail.com"
>
> > <Antti.Luk...@googlemail.com> wrote:
>
> > > MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> > > ram!)
> > > so it is also bad idea to use reference to it for marketing. unless..=
.
>
> > Does Altera have *any* FPGAs with distributed ram? =A0I thought that
> > distributed ram (using the LUT ram as real ram) was patented by Xilinx
> > although Lattice has a license to use it (they got it when they bought
> > the Lucent ORCA line which Lucent licensed from Xilinx). =A0I think thi=
s
> > patent is still in force although it is likely reaching its end of
> > life in a very few years.
>
> > I think distributed ram is much less important now although I will say
> > it can come in handy. =A0I am looking at using it in a possible design,
> > not in place of the block ram, but because I don't have enough block
> > ram! =A0I need a sizable delay line and I need another 208 bytes of
> > delay. =A0So I'll use 104 LUTs in a serial chain along with two blocks
> > of ram. =A0That will leave 4 blocks for the on chip CPU.
>
> > > unless your processor could work with MAXII and not external
> > > components!!
>
> > > I do have a MAXII optimized processor design that fits <240 MAXII LE'=
s
> > > and is useable, but it was real hard design and compromise to get
> > > it useable at all. Very small soft-cores are possible and useable as
> > > example Actel CoreABC can be optimized by GUI settingsto very
> > > very low logic utilization.
>
> > Is your CPU available to view? =A0I am always interested in a decent CP=
U
> > design for FPGAs.
>
> > > your SD card boot mentioned, have you ever tried it on real FPGA?
> > > the CoreABC SD card init worked the VERY first time tested on
> > > real FPGA with real SD. And it was programmed in assembler.
> > > in Assembler for a architecture previously unknown to me.
>
> > I am very interested in any code to access SD cards. =A0One idea I woul=
d
> > like to put into place is to put a
> > CPU in my test fixture FPGA which would read a bit stream from the SD
> > card and program the FPGA on the target board/UUT. =A0Then it would rea=
d
> > a second file which contains the test procedure and conduct the test
> > of the UUT. =A0I'm not certain that I can do this because I am sharing =
I/
> > O lines between the SD card and some RS-422 chips used to test the
> > UUT. =A0So the SD card would have to be removed and then plugged back i=
n
> > for every card. =A0Still, I would be interested in your code, or even
> > just the info you used to understand how to read it. =A0I assume you ar=
e
> > using a file system and not just treating the SD as a flash memory.
>
> > > I am still looking for a good small soft-core, and well it seem
> > > not to exist...
>
> > I seem to recall that you were trying to find a bit serial CPU that
> > would be the smallest possible in an FPGA. =A0Did you ever find one you
> > liked? =A0Personally, I think that is a goal with a very low target
> > application size. =A0But certainly there are some apps where this could
> > be useful.
>
> > My potential app might will work with such a processor. =A0It will be
> > receiving 16 bit data at a 1 kHz rate which it will decode into a 200
> > bps bit stream with 2 bits per symbol at 100 Hz symbol rate (and/or
> > the other direction). =A0That is pretty low bandwidth. =A0A potential
> > future app would be the same algorithm at 10x the data rates.
>
> > My existing processor design was using around 600 LUTs in an Altera
> > ACEX 1K part. =A0I have not yet ported it to my new target, a Lattice X=
P
> > device (block ram, but no multipliers). =A0If I take out some of the
> > stuff intended for debugging, it might be as small as 400 LUTs, but I
> > can't be sure just yet.
>
> > Rick
>
> Hi Rick,
>
> my CPU is available for view, if i find it again.. its on the search
> path over 6 external HDD's
>
> as of distributed RAM it looks the patent is hold by:
>
> Altera Corporation, not Xilinx
>
> http://www.freepatentsonline.com/5352940.html
>
> but maybe i need sunglasses


Look into FLEX8000 etc architecture. The reason for MAXII design is I
have a MAXII 1270 Devkit (PCI/USB one). Then the 570 IIZ chips came
out and I wondered if I could make something that small, I can say the
extra restriction of the 570 helped in reducung logic count, even
though I'll use 1270 for any possible product.

It is possible to remove the IO programmable, and the instruction
counter to lower logic count. Also removing the UFM_parallel mega
block would cause a significant logic reduction. So if you arrange
your own IO forrget the ufm 512 flash (ROM), the bidirectionality of
the IO and don't need clock counting, then there would be space for
some RAM.

The patent quoted relates to using RAM as PLA or RAM.

cheers jacko

hi

292 LEs fully stripped, no ROM, no RAM no IO pins, 16 bit address, 16
bit data Bus. Expected 20-30MHz, (36 pins plus power), About 10 MIPS
at 20MHz.

cheers jacko

On Mar 12, 7:30=A0pm, Jacko <jackokr...@gmail.com> wrote:
> hi
>
> 292 LEs fully stripped, no ROM, no RAM no IO pins, 16 bit address, 16
> bit data Bus. Expected 20-30MHz, (36 pins plus power), About 10 MIPS
> at 20MHz.
>
> cheers jacko

without any io/ram/rom its kinda useless?
and such small soft cores can usually run 200mhz+ in decent FPGA's ;)
(150mhz in low cost FPGA's)

ok, 292 or <570LE, it's ir-relevant as long as there are no tools to
program it,
and your forth-xxx whatever isnt useable yet?

there are zillions of stack soft-cpu's but i fail to see nice and easy
tools
todo anything with them.. no compilers
some forth xxx things that requires some xxx to be installed on your
PC
and then do something very awkward and some more to get some code
actually executing...

and yes I have programmed in Forth many decades ago, think used
something called GraphForth for msdos

=3D=3D

compile_my_forth_to_bin.exe hello.forth > hello.bin

if that creates a ready to use bin file to run with your nibz
and you have tons of tested libraries.. someone may get interested..

if you have something totally untested, not ready no demos
no reference design ?

=3D=3D

ok ZPU (a stack machine also) has GCC toolchain kind of, but it isnt
that small anymore the core despite being advertized as smallest 32
bit core with GCC support

Antti

On Mar 11, 10:34 pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
>
> MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> ram!)
>
> Antti

Perhaps that explains why Altera markets it as a CPLD, not an FPGA?

AL

Jim

You beat me to the comment on serial processors.

A long time ago I designed a number of bit serial processors
they can be very hardware efficient. There are a number of
very clever math algorithms that take advantage of bit serial.

A second comment on this core is what thought has been made
on parallel partitioning problems and how would that be handled.

Regards,

--
Walter Banks
Byte Craft Limited
http://www.bytecraft.com



-jg wrote:

> On Mar 12, 8:57 pm, rickman <gnu...@gmail.com> wrote:
> > I seem to recall that you were trying to find a bit serial CPU that
> > would be the smallest possible in an FPGA.  Did you ever find one you
> > liked?  Personally, I think that is a goal with a very low target
> > application size.  But certainly there are some apps where this could
> > be useful.
>
> Bit-serial (like Cop8) only makes size-sense to simplify bus routing.
> - but that's almost free in a FPGA, so other needs better drive Bit-
> Serial.
>
> Bit-serial Multiply/divide can save resource, but that's less a core
> than
> an algortihm  trade-off, and Mul/Div are rare in the smallest cores
> anyway.
>
> One plus that appeals to me, is Execute from Serial FLASH, (and now
> Serial RAM)
> [does a nibble fetch from 4 bit SPI still count as Bit-serial ? ]
>  as resource space. Saves MANY pins, and PCB space, but I'm not sure
> the
> core will be _smaller_ as a result - more likely slightly larger ?
>
> -jg

On Mar 13, 8:12=A0am, Walter Banks <wal...@bytecraft.com> wrote:
> Jim
>
> You beat me to the comment on serial processors.
>
> A long time ago I designed a number of bit serial processors
> they can be very hardware efficient. There are a number of
> very clever math algorithms that take advantage of bit serial.

The obvious next question, is do you have compilers
& maths libraries for such an animal ? ;)

-jg

On Mar 12, 8:17=A0pm, LittleAlex <alex.lo...@email.com> wrote:
> On Mar 11, 10:34 pm, "Antti.Luk...@googlemail.com"
>
> <Antti.Luk...@googlemail.com> wrote:
>
> > MAXII is a bad FPGA, as Altera made design mistakes (no distributed
> > ram!)
>
> > Antti
>
> Perhaps that explains why Altera markets it as a CPLD, not an FPGA?
>
> AL

its bad when marketed as CPLD as well ;)

because it looks like poor man FPGA...

Antti

Hi

12 bit (4K) 230 LEs 28 pin + Power 20-30MHz

nibz12-bit.vhd from download http://nibz.googlecode.com if you only
need a 4K address space of 12 bit memory locations. Full 12 bit
datapath. There is no benefit really going lower in the wide generic,
as an 8-bit only has 256 addressable locations for program and data.

cheers jacko

p.s. main reason for slowness is C% grade measure and use of carry
chain to reduce ALU area.

On Mar 12, 12:31=A0pm, -jg <Jim.Granvi...@gmail.com> wrote:
> On Mar 12, 8:57=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > I seem to recall that you were trying to find a bit serial CPU that
> > would be the smallest possible in an FPGA. =A0Did you ever find one you
> > liked? =A0Personally, I think that is a goal with a very low target
> > application size. =A0But certainly there are some apps where this could
> > be useful.
>
> Bit-serial (like Cop8) only makes size-sense to simplify bus routing.
> - but that's almost free in a FPGA, so other needs better drive Bit-
> Serial.
>
> Bit-serial Multiply/divide can save resource, but that's less a core
> than
> an algortihm =A0trade-off, and Mul/Div are rare in the smallest cores
> anyway.
>
> One plus that appeals to me, is Execute from Serial FLASH, (and now
> Serial RAM)
> [does a nibble fetch from 4 bit SPI still count as Bit-serial ? ]
> =A0as resource space. Saves MANY pins, and PCB space, but I'm not sure
> the
> core will be _smaller_ as a result - more likely slightly larger ?
>
> -jg

Jim,

this almost the old discussion ;)

yes, a bit serial processor that executes in place either from spi
flash or SD card
and uses say the dual 512 data buffers of atmel dataflash as ram could
be
very low resources

say for lowest cost Xilinx FPGA S3A-50 resources are pretty tight, so
if
a soft core can execute from the same spi flash that is used for
config
using the flash as code memory and flash buffers as ram, it would
retain almost all the rest of the FPGA resources for user application

should be doable in <100 Xilinx s3a slices i think

Antti