Forums

Best way to write to LUT based CPLD from slow CPU?

Started by Unknown March 11, 2009
Hi,
  I am inexperienced in CPLD design. I am using a slow CPU (PC ISA
port) and LUT based CPLD (Altera MAX II) in my design. I implemented
many control registers (implemented with D FF) in the CPLD that the
CPU will write from time to time. The ISA bus is slow, with a write
cycle of several hundred ns. The CPLD is running on 50ns primary
clock.

I am facing two choices of implementing the register writing signals.
1. The WRITE\ (active low) signal as a secondary global clock. The CS\
and address lines will be decoded into ENABLE signal for those D FFs.
The drawback is that I will have two clock domains in the same chip.
This was the approach I took, but now I start to be suspicious about
it.
2. The WRITE\, CS\, address lines as regular signals, are synced first
to the 50ns clock, and then decoded into ENABLE signals for those D
FFs. Since the ISA write cycle is much longer than 50ns, I guess this
strategy will work too.

Please help me to make the right decision. What is the common approach
people take for this kind of problem? Thank you.

vax9000
On Wed, 11 Mar 2009 11:49:03 -0700 (PDT), VAX9000@gmail.com wrote:

>Hi, > I am inexperienced in CPLD design. I am using a slow CPU (PC ISA >port) and LUT based CPLD (Altera MAX II) in my design. I implemented >many control registers (implemented with D FF) in the CPLD that the >CPU will write from time to time. The ISA bus is slow, with a write >cycle of several hundred ns. The CPLD is running on 50ns primary >clock. > >I am facing two choices of implementing the register writing signals.
You can't be VERY inexperienced - you are asking the right question :-) The ISA bus is so dog-slow that it is almost certainly easiest to oversample the write strobe and use that to establish a write-enable, synchronous to the internal 20MHz clock, occurring at a time when you know that the write address and data are stable. If the write strobe is shorter than 3 internal clock cycles, it's not safe to do oversampling and instead you need to implement a handshake across the clock domains. This is sure to be more troublesome, although it's not too hard. Good luck! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
On Mar 11, 3:00=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 11 Mar 2009 11:49:03 -0700 (PDT), VAX9...@gmail.com wrote: > >Hi, > > =A0I am inexperienced in CPLD design. I am using a slow CPU (PC ISA > >port) and LUT based CPLD (Altera MAX II) in my design. I implemented > >many control registers (implemented with D FF) in the CPLD that the > >CPU will write from time to time. The ISA bus is slow, with a write > >cycle of several hundred ns. The CPLD is running on 50ns primary > >clock. > > >I am facing two choices of implementing the register writing signals. > > You can't be VERY inexperienced - you are asking the right > question :-) >
Thank you for your answer. I am an experienced TTL amateur designer, but CPLD or FPGA is different, especially when I could not watch the resulted routing because I am using the free web- software. It is like working in the darkness with a pair of sunglasses.
> The ISA bus is so dog-slow that it is almost certainly > easiest to oversample the write strobe and use that to > establish a write-enable, synchronous to the internal 20MHz > clock, occurring at a time when you know that the write > address and data are stable. > > If the write strobe is shorter than 3 internal clock cycles, > it's not safe to do oversampling and instead you need to > implement a handshake across the clock domains. =A0This is > sure to be more troublesome, although it's not too hard. >
I think you suggested the single clock domain solution. I will give it a try. Thank you!
> Good luck! > -- > Jonathan Bromley, Consultant
On Mar 11, 3:34=A0pm, VAX9...@gmail.com wrote:
> On Mar 11, 3:00=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > On Wed, 11 Mar 2009 11:49:03 -0700 (PDT), VAX9...@gmail.com wrote: > > >Hi, > > > =A0I am inexperienced in CPLD design. I am using a slow CPU (PC ISA > > >port) and LUT based CPLD (Altera MAX II) in my design. I implemented > > >many control registers (implemented with D FF) in the CPLD that the > > >CPU will write from time to time. The ISA bus is slow, with a write > > >cycle of several hundred ns. The CPLD is running on 50ns primary > > >clock. > > > >I am facing two choices of implementing the register writing signals. > > > You can't be VERY inexperienced - you are asking the right > > question :-) > > Thank you for your answer. I am an experienced TTL amateur designer, > but CPLD or FPGA is different, especially when I could not watch the > resulted routing because I am using the free web- software. It is like > working in the darkness with a pair of sunglasses. > > > The ISA bus is so dog-slow that it is almost certainly > > easiest to oversample the write strobe and use that to > > establish a write-enable, synchronous to the internal 20MHz > > clock, occurring at a time when you know that the write > > address and data are stable. > > > If the write strobe is shorter than 3 internal clock cycles, > > it's not safe to do oversampling and instead you need to > > implement a handshake across the clock domains. =A0This is > > sure to be more troublesome, although it's not too hard. > > I think you suggested the single clock domain solution. I will give it > a try. Thank you!
I agree. A single clock domain solves so many problems, or more accurately, focuses all of the problems into one, well defined area, the sampling of the incoming signals. 50 ns is fast enough that you can sample with two FFs on opposite edges of the 50 ns clock and get excellent metastability rejection. I did a similar design once and did just that. I don't remember my clock rate, but it actually varied between a fast clock and a slow rate of around 2 MHz. This allowed the power consumption of the circuit to be greatly reduced. I used a very tricky design to make it work while the clock ranged between slower and faster than the bus rate. I don't recall the details (it was some 8 years ago), but if you need it, I could dig it up. If you want to do this yourself for fun, then go for it! BTW, when I couldn't remember how I solved that problem, it cost me a job offer. I spoke with the head of a small/mid sized company and he asked me to describe a tough design problem I had solved and to describe my thought process. I immediately thought of this one, since it took me two days to figure out how to do it, but couldn't remember how I solved it!!! Needless to say he was not impressed. He wouldn't let me switch to another one either. I had to stand in front of the chalk board and look stupid for some 10 minutes while I failed to have any idea of how I made that work. And I'm not very used to feeling stupid when it doesn't involve the other gender ;^) Needless to say, I didn't get an offer from these guys. That never used to happen to me either. Maybe it was age discrimination... yeah, that's the ticket! Rick