Virtex 5 LVDS

Hi

I am routing a pcb with some LVDS signals. Is there a way in Virtex 5 to
invert the signal so that I can have P->N and N->P on the pcb.

Cheers

Jon

"maxascent" <maxascent@yahoo.co.uk> wrote in message 
news:0tSdnaEyPIToVSbU4p2dnAA@giganews.com...
> Hi
>
> I am routing a pcb with some LVDS signals. Is there a way in Virtex 5 to
> invert the signal so that I can have P->N and N->P on the pcb.

Generally, yes.  Just invert the data in your logic. 

I thought there may be a way to do it in the IOB rather than have to use
some logic. 

>
>"maxascent" <maxascent@yahoo.co.uk> wrote in message 
>news:0tSdnaEyPIToVSbU4p2dnAA@giganews.com...
>> Hi
>>
>> I am routing a pcb with some LVDS signals. Is there a way in Virtex 5
to
>> invert the signal so that I can have P->N and N->P on the pcb.
>
>Generally, yes.  Just invert the data in your logic. 
>
>
>

Hello,

Yes, the Virtex-5 IOB supports inversion of any input signal (LVDS or
single ended) prior to the IOB flip-flop in the ILOGIC component.

This feature is unique to Virtex-5 - Virtex-4 doesn't have it and
you'd have to use a tiny bit of the logic fabric of the part.

- Nathan

On Mar 14, 12:47=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I thought there may be a way to do it in the IOB rather than have to use
> some logic.
>
>
>
>
>
> >"maxascent" <maxasc...@yahoo.co.uk> wrote in message
> >news:0tSdnaEyPIToVSbU4p2dnAA@giganews.com...
> >> Hi
>
> >> I am routing a pcb with some LVDS signals. Is there a way in Virtex 5
> to
> >> invert the signal so that I can have P->N and N->P on the pcb.
>
> >Generally, yes. =A0Just invert the data in your logic.

Nathan

Do you happen to know how you enable this inverter? I have looked in a few
documents but cant find how to enable it. There is mention of it in XAPP873
so I know it is possible.

Cheers

Jon

"maxascent" <maxascent@yahoo.co.uk> wrote:

>Nathan
>
>Do you happen to know how you enable this inverter? I have looked in a few
>documents but cant find how to enable it. There is mention of it in XAPP873
>so I know it is possible.

in VHDL:
a <= not b;

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

Hi

I dont want to infer additional logic in the fpga but use the inverter
built into the IOB. I'm not sure that using that construct will work.

Jon

On Mar 15, 3:38=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> Hi
>
> I dont want to infer additional logic in the fpga but use the inverter
> built into the IOB. I'm not sure that using that construct will work.
>
> Jon

it should.

all inverters should be pushed into the primitives if the inversion is
available
if the tools cant do this its the tools that are rotten.
should be no need todo any magic

Antti

"maxascent" <maxascent@yahoo.co.uk> wrote:

>Hi
>
>I dont want to infer additional logic in the fpga but use the inverter
>built into the IOB. I'm not sure that using that construct will work.

The synthesizer will deal with it. Just be sure the timing constraints
are properly specified so the synthesizer has no other choice than
using the inverter in the IOB. BTW, most XIlinx primitives have
inverters on their inputs.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------