I recently read the thread started by Jonathan Bromley, titled "Is this phase accumulator trick well-known???". I am building a DPLL and I will be using this technique. I am using a FIFO to delay data by a fixed time where the data is clocked in and out on variable rate clocks. The two clocks run at the same average rate, the input clock is gapped and the output clock is generated by the PLL to match the average of the input clock. By "clocks" I really mean clock enable just so we don't get into a big discussion on metastability and such. The requirement for a fixed time delay with a variable clock means I need to adjust the amount of data held in the FIFO as the clock speed changes. It seems to me like a proportional control of the PLL feedback using the FIFO data count will do just what I am looking for. I did some calcs and I know exactly how much data needs to be held at each clock rate. So I am going to design the phase accumulator so that the data count is used as the phase increment value. I have not analyzed the dynamic characteristics of this circuit yet, but that will be next. I just thought it was fortuitous that this discussion had come up recently to remind me of this circuit design. I worked with phase accumulators and NCOs some time back, but had forgotten most of the details. If that thread has not been posted I may well have forgotten the technique of setting the accumulator modulus to control the scale of the phase increment. Thanks! Rick
Well Known? Phase Accumulator Trick
Started by ●March 15, 2009
Reply by ●March 16, 20092009-03-16
On Sun, 15 Mar 2009 12:31:01 -0700 (PDT), rickman wrote: [...]>If that thread has not been posted I may well have forgotten >the technique [...]Somehow I suspect that you would have worked it all out for yourself, postings or no postings. But your point is well made. I'm often astonished at the way information picked up long ago turns out to be useful in unexpected contexts (I guess that's called "experience"); and a little memory-jogger is usually needed to bring it all back (I guess that's called "forgetfulness"). -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
