Zero operand CPUs

Maybe it's you ;)
> > Man, some people just don't get it.

Regarding my real name: Helmar.

What you and others not get is: "Zero Operand Cpu" is something like
"Wir sind Papst!" in Germany. Why did not FORTH INC., forth.com make
advertise with "The Zero-Operand Language!" all the last years? It
would save a lot of time for programmers, not to care about operands.
I guess they do not for good reasons.

-Helmar (...censored...)

On Mar 18, 7:54=A0pm, Jacko <jackokr...@gmail.com> wrote:
> On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > \ FORTH Assembler for nibz
> > > \
> > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > \ This file is part of Gforth.
>
> > > \ Gforth is free software; you can redistribute it and/or
> > > \ modify it under the terms of the GNU General Public License
> > > \ as published by the Free Software Foundation, either version 3
> > > \ of the License, or (at your option) any later version.
>
> > > \ This program is distributed in the hope that it will be useful,
> > > \ but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See the
> > > \ GNU General Public License for more details.
>
> > > \ You should have received a copy of the GNU General Public License
> > > \ along with this program. If not, seehttp://www.gnu.org/licenses/.
> > > \
> > > \ Autor: =A0 =A0 =A0 =A0 =A0Simon Jackson, BEng.
> > > \
> > > \ Information:
> > > \
> > > \ - Simple Assembler
>
> > > \ only forth definitions
>
> > > require asm/basic.fs
>
> > > =A0also ASSEMBLER definitions
>
> > > require asm/target.fs
>
> > > =A0HERE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( Begin )
>
> > > \ The assembler is very simple. All 16 opcodes are
> > > \ defined immediate so they can be inlined into colon defs.
>
> > > \ primary opcode constant writers
>
> > > : BA 0 , ; immediate
> > > : FI 1 , ; immediate
> > > : RI 2 , ; immediate
> > > : SI 3 , ; immediate
>
> > > : DI 4 , ; immediate
> > > : FA 5 , ; immediate
> > > : RA 6 , ; immediate
> > > : SA 7 , ; immediate
>
> > > : BO 8 , ; immediate
> > > : FO 9 , ; immediate
> > > : RO 10 , ; immediate
> > > : SO 11 , ; immediate
>
> > > : SU 12 , ; immediate
> > > : FE 13 , ; immediate
> > > : RE 14 , ; immediate
> > > : SE 15 , ; immediate
>
> > > =A0HERE =A0SWAP -
> > > =A0CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > What instruction is a CALL? =A0How do you specify the address? =A0How d=
o
> > you specify literal data?
>
> > Rick
>
> $addr ,

Jacko

your comments are just getting more and more fuzzy and cryptic.

is that on purpose?

Antti

On Mar 18, 2:42=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Mar 18, 7:54=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
>
>
>
>
> > On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
> > > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > > \ FORTH Assembler for nibz
> > > > \
> > > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > > \ This file is part of Gforth.
>
> > > > \ Gforth is free software; you can redistribute it and/or
> > > > \ modify it under the terms of the GNU General Public License
> > > > \ as published by the Free Software Foundation, either version 3
> > > > \ of the License, or (at your option) any later version.
>
> > > > \ This program is distributed in the hope that it will be useful,
> > > > \ but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See the
> > > > \ GNU General Public License for more details.
>
> > > > \ You should have received a copy of the GNU General Public License
> > > > \ along with this program. If not, seehttp://www.gnu.org/licenses/.
> > > > \
> > > > \ Autor: =A0 =A0 =A0 =A0 =A0Simon Jackson, BEng.
> > > > \
> > > > \ Information:
> > > > \
> > > > \ - Simple Assembler
>
> > > > \ only forth definitions
>
> > > > require asm/basic.fs
>
> > > > =A0also ASSEMBLER definitions
>
> > > > require asm/target.fs
>
> > > > =A0HERE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( Begin )
>
> > > > \ The assembler is very simple. All 16 opcodes are
> > > > \ defined immediate so they can be inlined into colon defs.
>
> > > > \ primary opcode constant writers
>
> > > > : BA 0 , ; immediate
> > > > : FI 1 , ; immediate
> > > > : RI 2 , ; immediate
> > > > : SI 3 , ; immediate
>
> > > > : DI 4 , ; immediate
> > > > : FA 5 , ; immediate
> > > > : RA 6 , ; immediate
> > > > : SA 7 , ; immediate
>
> > > > : BO 8 , ; immediate
> > > > : FO 9 , ; immediate
> > > > : RO 10 , ; immediate
> > > > : SO 11 , ; immediate
>
> > > > : SU 12 , ; immediate
> > > > : FE 13 , ; immediate
> > > > : RE 14 , ; immediate
> > > > : SE 15 , ; immediate
>
> > > > =A0HERE =A0SWAP -
> > > > =A0CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > > What instruction is a CALL? =A0How do you specify the address? =A0How=
 do
> > > you specify literal data?
>
> > > Rick
>
> > $addr ,
>
> Jacko
>
> your comments are just getting more and more fuzzy and cryptic.
>
> is that on purpose?
>
> Antti

$addr , is not in conflict with a CALL. For a literal Jacko has to
answer for my understandings.

Regards,
-Helmar

On Mar 18, 3:51=A0pm, Jacko <jackokr...@gmail.com> wrote:
> On 18 Mar, 11:48, "Antti.Luk...@googlemail.com"
>
>
>
> <Antti.Luk...@googlemail.com> wrote:
> > On Mar 18, 8:45=A0am, rickman <gnu...@gmail.com> wrote:
>
> > > On Mar 17, 7:06=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
> > > > There is now a link on the instruction set page presenting an engli=
sh
> > > > text description of the BO instruction. All other instructions foll=
ow
> > > > a similar symbology.
>
> > > Dude, you are really terrible at this. =A0In one place you tell peopl=
e
> > > about a CPU you designed with no specifics. =A0Another place you post=
 a
> > > link to a web page with very fuzzy descriptions of the instruction se=
t
> > > that is not usable. =A0Then here you post that you have added some mo=
re
> > > explanation, but no link. =A0Are we supposed to search around to find
> > > the link to your web page again? =A0I have no idea where to find it.
>
> > > I may not be very tactful, but I really am trying to help you, not be
> > > insulting. =A0I hope it doesn't come off that way.
>
> > > Rick
>
> > You are so right...
> > I looked (again) the nibz web
>
> > downloaded the most promising document (tagged FEATURED!)
>
> > did not understand much, scrolled to the end of the document..
> > where on the last line stands:
>
> > ".... ummmm ...."
>
> > guess this is what we all should be doing: ummmmmmm
>
> The umm does make sense in terms of what the document was describing.
>

Jacko:

....ummmmm....

does NEVER make sense in a document describing an IP core.

not in my world (sure maybe i live in the wrong one)

Antti

zwsdotcom@gmail.com wrote:
> 
> On Mar 18, 9:06 am, Helmar <hel...@gmail.com> wrote:
> 
> > What do you expect from something that does not need operands or has
> 
> Studying first-year computer science (machine architecture) might be
> helpful to you, since this is very standard terminology. Of course
> relatively few people have worked on zero-operand ISAs but I guess
> most people in this NG have worked extensively with 1- and 2-operand
> machines, and probably 3-operand also.

I suppose, most have worked with a 0-, 1-, 1 1/2-, 2-, 3- and 3*1/2 
ADDRESS machines but none with a 0- or 1- OPERAND machine.

An add instruction always needs two operands and has one results.
But if you use a predefined location (stack, accu) for some of them 
then you can omit the address information in the instruction.

Herbert Kleebauer schreef:
> zwsdotcom@gmail.com wrote:
>> On Mar 18, 9:06 am, Helmar <hel...@gmail.com> wrote:
>>
>>> What do you expect from something that does not need operands or has
>> Studying first-year computer science (machine architecture) might be
>> helpful to you, since this is very standard terminology. Of course
>> relatively few people have worked on zero-operand ISAs but I guess
>> most people in this NG have worked extensively with 1- and 2-operand
>> machines, and probably 3-operand also.
> 
> I suppose, most have worked with a 0-, 1-, 1 1/2-, 2-, 3- and 3*1/2 
> ADDRESS machines but none with a 0- or 1- OPERAND machine.
> 
> An add instruction always needs two operands and has one results.
> But if you use a predefined location (stack, accu) for some of them 
> then you can omit the address information in the instruction.


Maybe 'implicit operand' would be a more accurate description.

"David Brown" <david@westcontrol.removethisbit.com> wrote in message 
news:49bfc0c7$0$14779$8404b019@news.wineasy.se...
> rickman wrote:
>>
>> BTW, ZPU may have a GCC compiler, but without a debugger, is that
>> really useful?  There aren't many projects done in C that are debugged
>> without an emulator.
>>
>
> It's possible to do a lot of development without a debugger.  I often do 
> embedded development without one (though I prefer to have one available if 
> possible).  Until you've done debugging with only a single LED for 
> signalling, you haven't really done embedded development.  Bonus points if 
> the microcontroller you're using only comes in OTP version.

Ooh yeah - been there, done that. Big believer in the idea that if it's 
designed right, all you have to worry about is typos.

Haven't used an ICE (or a debugger) in about 25 years.

Steve
--
http://www.fivetrees.com 

"Dombo" <dombo@disposable.invalid> wrote in message 
news:49c15f65$0$28145$5fc3050@news.tiscali.nl...
>
> Maybe 'implicit operand' would be a more accurate description.

That is almost the first sensible comment I've read in this thread.

Steve
--
http://www.fivetrees.com 

On Mar 18, 1:54=A0pm, Jacko <jackokr...@gmail.com> wrote:
> On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > \ FORTH Assembler for nibz
> > > \
> > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > \ This file is part of Gforth.
>
> > > \ Gforth is free software; you can redistribute it and/or
> > > \ modify it under the terms of the GNU General Public License
> > > \ as published by the Free Software Foundation, either version 3
> > > \ of the License, or (at your option) any later version.
>
> > > \ This program is distributed in the hope that it will be useful,
> > > \ but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See the
> > > \ GNU General Public License for more details.
>
> > > \ You should have received a copy of the GNU General Public License
> > > \ along with this program. If not, seehttp://www.gnu.org/licenses/.
> > > \
> > > \ Autor: =A0 =A0 =A0 =A0 =A0Simon Jackson, BEng.
> > > \
> > > \ Information:
> > > \
> > > \ - Simple Assembler
>
> > > \ only forth definitions
>
> > > require asm/basic.fs
>
> > > =A0also ASSEMBLER definitions
>
> > > require asm/target.fs
>
> > > =A0HERE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( Begin )
>
> > > \ The assembler is very simple. All 16 opcodes are
> > > \ defined immediate so they can be inlined into colon defs.
>
> > > \ primary opcode constant writers
>
> > > : BA 0 , ; immediate
> > > : FI 1 , ; immediate
> > > : RI 2 , ; immediate
> > > : SI 3 , ; immediate
>
> > > : DI 4 , ; immediate
> > > : FA 5 , ; immediate
> > > : RA 6 , ; immediate
> > > : SA 7 , ; immediate
>
> > > : BO 8 , ; immediate
> > > : FO 9 , ; immediate
> > > : RO 10 , ; immediate
> > > : SO 11 , ; immediate
>
> > > : SU 12 , ; immediate
> > > : FE 13 , ; immediate
> > > : RE 14 , ; immediate
> > > : SE 15 , ; immediate
>
> > > =A0HERE =A0SWAP -
> > > =A0CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > What instruction is a CALL? =A0How do you specify the address? =A0How d=
o
> > you specify literal data?
>
> > Rick
>
> $addr ,

How many bits are in an opcode, 4 or 5?  I would say it has to be five
or there is no way for the machine to distinguish between an opcode
and an address.  In other words, there *has* to be a CALL instruction,
even if it is just a one bit opcode with the rest being the address.

Rick

On Mar 18, 4:48=A0pm, Herbert Kleebauer <k...@unibwm.de> wrote:
> zwsdot...@gmail.com wrote:
>
> > On Mar 18, 9:06 am, Helmar <hel...@gmail.com> wrote:
>
> > > What do you expect from something that does not need operands or has
>
> > Studying first-year computer science (machine architecture) might be
> > helpful to you, since this is very standard terminology. Of course
> > relatively few people have worked on zero-operand ISAs but I guess
> > most people in this NG have worked extensively with 1- and 2-operand
> > machines, and probably 3-operand also.
>
> I suppose, most have worked with a 0-, 1-, 1 1/2-, 2-, 3- and 3*1/2
> ADDRESS machines but none with a 0- or 1- OPERAND machine.
>
> An add instruction always needs two operands and has one results.
> But if you use a predefined location (stack, accu) for some of them
> then you can omit the address information in the instruction.

Everyone here who is objecting to the concept of a zero-operand CPU
seems to be defining the term for themselves and then arguing about
it.  A zero-operand instruction set is not one where the operators
*have* no operands.  It is one where the instruction has to *specify*
no explicit operands.  The operands are ***implied*** by the
architecture of the machine.  e.g. a stack machine can use the top two
elements of the stack as the operands and can put the result back on
the stack.  No operands need to be *specified* because that is
*implied* in the architecture.

Why would anyone want to argue about the name of a concept rather than
to *ask* someone to explain the concept?

Rick