Zero operand CPUs

On Mar 19, 4:52=A0am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
> >I am finding that none of this is truly obvious and may not always be
> >true. =A0Real world testing and comparisons are in order, real tests
> >that we can all see and understand...
>
> Back in the 70s, Xerox had the Mesa world running on Altos.
> It was a stack based architecture. =A0The goal was to reduce
> code space. =A0(That was back before people figured out that
> Moore's law was going to make code size not very interesting.)

Not entirely true.  Code size is still an issue when a CPU is being
built in a small FPGA or there are a number of them in most any FPGA.
In an FPGA, memory is still a limited resource.


> Given the available technology of the time, it worked great.
>
> In addition to the stack (I think it was 5 or 6 registers)
> there was a PC, a module pointer for global variables, and a
> frame pointer for this procedure context.
>
> The opcodes were implemented in microcode rather than gates,
> so there was a lot of flexibility in assigning values.
>
> Calls were fancy, but the simple case allocated a frame
> off the free list, setup the return link and such.
>
> Most of the opcodes were loads. =A0It was a 16 bit system, but
> there was a lot of support for 32 bit arithmetic and pointers.
>
> Excpet in rare occasions when you were hacking on the system,
> we didn't care about the details of the architecture. =A0Code
> is code. =A0The basic ideas don't change because the architecture
> changes. =A0You have loads, stores, loops, adds, muls...
> =A0 y =3D a*x+b
> turns into (handwave)
> =A0 load a
> =A0 load x
> =A0 mul
> =A0 load b
> =A0 add
> =A0 store y
>
> Some people call "load" push. =A0If a or b are constants,
> the load might be a load immediate...
>
> It might be a little weird if you wanted to write assembly code.
> I think I'd get used to it if I had some good examples to learn
> from. =A0(I've writted quite a bit of microcode back in the old
> days and some Forth recently.) =A0If you have a good complier
> you never think about that stuff.

Why write in assembly then?  I seem to recall that HP made some
machines that were stack based.  A friend had a job of digging through
core dumps to figure out why a program crashed.  I don't remember the
details, but he didn't do that for long before he got promoted out of
there.

Rick

On Mar 19, 9:26=A0am, Jacko <jackokr...@gmail.com> wrote:
> On 19 Mar, 00:38, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Mar 18, 1:54=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
> > > On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
> > > > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > > > \ FORTH Assembler for nibz
> > > > > \
> > > > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > > > \ This file is part of Gforth.
>
> > > > > \ Gforth is free software; you can redistribute it and/or
> > > > > \ modify it under the terms of the GNU General Public License
> > > > > \ as published by the Free Software Foundation, either version 3
> > > > > \ of the License, or (at your option) any later version.
>
> > > > > \ This program is distributed in the hope that it will be useful,
> > > > > \ but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See the
> > > > > \ GNU General Public License for more details.
>
> > > > > \ You should have received a copy of the GNU General Public Licen=
se
> > > > > \ along with this program. If not, seehttp://www.gnu.org/licenses=
/.
> > > > > \
> > > > > \ Autor: =A0 =A0 =A0 =A0 =A0Simon Jackson, BEng.
> > > > > \
> > > > > \ Information:
> > > > > \
> > > > > \ - Simple Assembler
>
> > > > > \ only forth definitions
>
> > > > > require asm/basic.fs
>
> > > > > =A0also ASSEMBLER definitions
>
> > > > > require asm/target.fs
>
> > > > > =A0HERE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( Begin )
>
> > > > > \ The assembler is very simple. All 16 opcodes are
> > > > > \ defined immediate so they can be inlined into colon defs.
>
> > > > > \ primary opcode constant writers
>
> > > > > : BA 0 , ; immediate
> > > > > : FI 1 , ; immediate
> > > > > : RI 2 , ; immediate
> > > > > : SI 3 , ; immediate
>
> > > > > : DI 4 , ; immediate
> > > > > : FA 5 , ; immediate
> > > > > : RA 6 , ; immediate
> > > > > : SA 7 , ; immediate
>
> > > > > : BO 8 , ; immediate
> > > > > : FO 9 , ; immediate
> > > > > : RO 10 , ; immediate
> > > > > : SO 11 , ; immediate
>
> > > > > : SU 12 , ; immediate
> > > > > : FE 13 , ; immediate
> > > > > : RE 14 , ; immediate
> > > > > : SE 15 , ; immediate
>
> > > > > =A0HERE =A0SWAP -
> > > > > =A0CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > > > What instruction is a CALL? =A0How do you specify the address? =A0H=
ow do
> > > > you specify literal data?
>
> > > > Rick
>
> > > $addr ,
>
> > How many bits are in an opcode, 4 or 5? =A0I would say it has to be fiv=
e
> > or there is no way for the machine to distinguish between an opcode
> > and an address. =A0In other words, there *has* to be a CALL instruction=
,
> > even if it is just a one bit opcode with the rest being the address.
>
> > Rick- Hide quoted text -
>
> > - Show quoted text -
>
> if(instructionRegister<16) doOpcode(instructionRegister) else
> doSubroutine(instructionRegister);

Ok, I'll bite, how wide is the instruction register and how does it
get loaded?

Getting straight (and complete) answers out of you is torture.

Rick

On 19 Mar, 13:40, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Mar 19, 3:26=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
>
>
>
>
> > On 19 Mar, 00:38, rickman <gnu...@gmail.com> wrote:
>
> > > On Mar 18, 1:54=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
> > > > On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
> > > > > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > > > > \ FORTH Assembler for nibz
> > > > > > \
> > > > > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > > > > \ This file is part of Gforth.
>
> > > > > > \ Gforth is free software; you can redistribute it and/or
> > > > > > \ modify it under the terms of the GNU General Public License
> > > > > > \ as published by the Free Software Foundation, either version =
3
> > > > > > \ of the License, or (at your option) any later version.
>
> > > > > > \ This program is distributed in the hope that it will be usefu=
l,
> > > > > > \ but WITHOUT ANY WARRANTY; without even the implied warranty o=
f
> > > > > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See t=
he
> > > > > > \ GNU General Public License for more details.
>
> > > > > > \ You should have received a copy of the GNU General Public Lic=
ense
> > > > > > \ along with this program. If not, seehttp://www.gnu.org/licens=
es/.
> > > > > > \
> > > > > > \ Autor: =A0 =A0 =A0 =A0 =A0Simon Jackson, BEng.
> > > > > > \
> > > > > > \ Information:
> > > > > > \
> > > > > > \ - Simple Assembler
>
> > > > > > \ only forth definitions
>
> > > > > > require asm/basic.fs
>
> > > > > > =A0also ASSEMBLER definitions
>
> > > > > > require asm/target.fs
>
> > > > > > =A0HERE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( Begin )
>
> > > > > > \ The assembler is very simple. All 16 opcodes are
> > > > > > \ defined immediate so they can be inlined into colon defs.
>
> > > > > > \ primary opcode constant writers
>
> > > > > > : BA 0 , ; immediate
> > > > > > : FI 1 , ; immediate
> > > > > > : RI 2 , ; immediate
> > > > > > : SI 3 , ; immediate
>
> > > > > > : DI 4 , ; immediate
> > > > > > : FA 5 , ; immediate
> > > > > > : RA 6 , ; immediate
> > > > > > : SA 7 , ; immediate
>
> > > > > > : BO 8 , ; immediate
> > > > > > : FO 9 , ; immediate
> > > > > > : RO 10 , ; immediate
> > > > > > : SO 11 , ; immediate
>
> > > > > > : SU 12 , ; immediate
> > > > > > : FE 13 , ; immediate
> > > > > > : RE 14 , ; immediate
> > > > > > : SE 15 , ; immediate
>
> > > > > > =A0HERE =A0SWAP -
> > > > > > =A0CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > > > > What instruction is a CALL? =A0How do you specify the address? =
=A0How do
> > > > > you specify literal data?
>
> > > > > Rick
>
> > > > $addr ,
>
> > > How many bits are in an opcode, 4 or 5? =A0I would say it has to be f=
ive
> > > or there is no way for the machine to distinguish between an opcode
> > > and an address. =A0In other words, there *has* to be a CALL instructi=
on,
> > > even if it is just a one bit opcode with the rest being the address.
>
> > > Rick- Hide quoted text -
>
> > > - Show quoted text -
>
> > if(instructionRegister<16) doOpcode(instructionRegister) else
> > doSubroutine(instructionRegister);
>
> > cheers jacko- Hide quoted text -
>
> > - Show quoted text -
>
> and how wide is instruction register?
>
> Antti- Hide quoted text -
>
> - Show quoted text -

Hi

The instruction register width like all register widths are controlled
by the generic parameter wide. if wide is 16 then 16 bit registers,
datapaths, addressable element size, alu, instruction width, in fact
all std_logic_vector of relavance are this generic width.

So if the generic wide is set to 4096 then a 4096 bit microprocessor
is rendered. Note the ALU will be slow until much if generate logic is
written in the VHDL.

As program and data memory address size is n bits and each addressable
is n-bits, then memory size is n^2 bits.

The useful knowledge of dividing the memory into optimized sections
such as say the microcode section at 4 bits wide only, saves on bits,
and means the instruction unpack logic is missing (no delays due to
it), yet the same density is achived, well better!!

This packing of the core 'microcode' to 4 bits is the main reason for
not having literal fetch as one might expect.

Then there is the next code layer, which is a threading list of
subroutine addresses and possibly literal values. This can be
compacted by using (m<n) m to n bit mapping, compression.

Then you have a data space of n bit wide memory.

Any other generics wanted??

cheers jacko

On Mar 19, 10:21 am, rickman <gnu...@gmail.com> wrote:
> On Mar 19, 9:26 am, Jacko <jackokr...@gmail.com> wrote:
>
>
>
> > On 19 Mar, 00:38, rickman <gnu...@gmail.com> wrote:
>
> > > On Mar 18, 1:54 pm, Jacko <jackokr...@gmail.com> wrote:
>
> > > > On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
> > > > > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > > > > \ FORTH Assembler for nibz
> > > > > > \
> > > > > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > > > > \ This file is part of Gforth.
>
> > > > > > \ Gforth is free software; you can redistribute it and/or
> > > > > > \ modify it under the terms of the GNU General Public License
> > > > > > \ as published by the Free Software Foundation, either version 3
> > > > > > \ of the License, or (at your option) any later version.
>
> > > > > > \ This program is distributed in the hope that it will be useful,
> > > > > > \ but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > > > > \ GNU General Public License for more details.
>
> > > > > > \ You should have received a copy of the GNU General Public License
> > > > > > \ along with this program. If not, seehttp://www.gnu.org/licenses/.
> > > > > > \
> > > > > > \ Autor:          Simon Jackson, BEng.
> > > > > > \
> > > > > > \ Information:
> > > > > > \
> > > > > > \ - Simple Assembler
>
> > > > > > \ only forth definitions
>
> > > > > > require asm/basic.fs
>
> > > > > >  also ASSEMBLER definitions
>
> > > > > > require asm/target.fs
>
> > > > > >  HERE                   ( Begin )
>
> > > > > > \ The assembler is very simple. All 16 opcodes are
> > > > > > \ defined immediate so they can be inlined into colon defs.
>
> > > > > > \ primary opcode constant writers
>
> > > > > > : BA 0 , ; immediate
> > > > > > : FI 1 , ; immediate
> > > > > > : RI 2 , ; immediate
> > > > > > : SI 3 , ; immediate
>
> > > > > > : DI 4 , ; immediate
> > > > > > : FA 5 , ; immediate
> > > > > > : RA 6 , ; immediate
> > > > > > : SA 7 , ; immediate
>
> > > > > > : BO 8 , ; immediate
> > > > > > : FO 9 , ; immediate
> > > > > > : RO 10 , ; immediate
> > > > > > : SO 11 , ; immediate
>
> > > > > > : SU 12 , ; immediate
> > > > > > : FE 13 , ; immediate
> > > > > > : RE 14 , ; immediate
> > > > > > : SE 15 , ; immediate
>
> > > > > >  HERE  SWAP -
> > > > > >  CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > > > > What instruction is a CALL?  How do you specify the address?  How do
> > > > > you specify literal data?
>
> > > > > Rick
>
> > > > $addr ,
>
> > > How many bits are in an opcode, 4 or 5?  I would say it has to be five
> > > or there is no way for the machine to distinguish between an opcode
> > > and an address.  In other words, there *has* to be a CALL instruction,
> > > even if it is just a one bit opcode with the rest being the address.
>
> > > Rick- Hide quoted text -
>
> > > - Show quoted text -
>
> > if(instructionRegister<16) doOpcode(instructionRegister) else
> > doSubroutine(instructionRegister);
>
> Ok, I'll bite, how wide is the instruction register and how does it
> get loaded?
>
> Getting straight (and complete) answers out of you is torture.
>
> Rick

Ok, I did the digging and found your instruction set doc as well as
the HDL.  I found that the IR is as wide as the rest of the machine.
This means that each instruction is N bits wide.  So on every opcode
that is one of the 16 instructions that are not calls, the real opcode
would be 0x000X in a 16 bit machine.  That is pretty durn inefficient
of program memory.  Your code size is going to suffer rather
severely.  Not only is each instruction large for a MISC machine,
because you only have 16 basic ops, you will need a lot of them.

So it would seem that this machine is slow (multi cycles to execute
one instruction and lots of instructions to do anything useful) as
well as inefficiently using code space.  Not what I would want to
consider for an ASIC, although if the docs are good enough it could be
worth it...  ;^)

Rick

On Mar 19, 4:28=A0pm, Jacko <jackokr...@gmail.com> wrote:
> On 19 Mar, 13:40, "Antti.Luk...@googlemail.com"
>
>
>
> <Antti.Luk...@googlemail.com> wrote:
> > On Mar 19, 3:26=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
> > > On 19 Mar, 00:38, rickman <gnu...@gmail.com> wrote:
>
> > > > On Mar 18, 1:54=A0pm, Jacko <jackokr...@gmail.com> wrote:
>
> > > > > On 18 Mar, 16:59, rickman <gnu...@gmail.com> wrote:
>
> > > > > > On Mar 18, 8:36 am, Jacko <jackokr...@gmail.com> wrote:
>
> > > > > > > \ FORTH Assembler for nibz
> > > > > > > \
> > > > > > > \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
>
> > > > > > > \ This file is part of Gforth.
>
> > > > > > > \ Gforth is free software; you can redistribute it and/or
> > > > > > > \ modify it under the terms of the GNU General Public License
> > > > > > > \ as published by the Free Software Foundation, either versio=
n 3
> > > > > > > \ of the License, or (at your option) any later version.
>
> > > > > > > \ This program is distributed in the hope that it will be use=
ful,
> > > > > > > \ but WITHOUT ANY WARRANTY; without even the implied warranty=
 of
> > > > > > > \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =A0See=
 the
> > > > > > > \ GNU General Public License for more details.
>
> > > > > > > \ You should have received a copy of the GNU General Public L=
icense
> > > > > > > \ along with this program. If not, seehttp://www.gnu.org/lice=
nses/.
> > > > > > > \
> > > > > > > \ Autor: =A0 =A0 =A0 =A0 =A0Simon Jackson, BEng.
> > > > > > > \
> > > > > > > \ Information:
> > > > > > > \
> > > > > > > \ - Simple Assembler
>
> > > > > > > \ only forth definitions
>
> > > > > > > require asm/basic.fs
>
> > > > > > > =A0also ASSEMBLER definitions
>
> > > > > > > require asm/target.fs
>
> > > > > > > =A0HERE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( Begin )
>
> > > > > > > \ The assembler is very simple. All 16 opcodes are
> > > > > > > \ defined immediate so they can be inlined into colon defs.
>
> > > > > > > \ primary opcode constant writers
>
> > > > > > > : BA 0 , ; immediate
> > > > > > > : FI 1 , ; immediate
> > > > > > > : RI 2 , ; immediate
> > > > > > > : SI 3 , ; immediate
>
> > > > > > > : DI 4 , ; immediate
> > > > > > > : FA 5 , ; immediate
> > > > > > > : RA 6 , ; immediate
> > > > > > > : SA 7 , ; immediate
>
> > > > > > > : BO 8 , ; immediate
> > > > > > > : FO 9 , ; immediate
> > > > > > > : RO 10 , ; immediate
> > > > > > > : SO 11 , ; immediate
>
> > > > > > > : SU 12 , ; immediate
> > > > > > > : FE 13 , ; immediate
> > > > > > > : RE 14 , ; immediate
> > > > > > > : SE 15 , ; immediate
>
> > > > > > > =A0HERE =A0SWAP -
> > > > > > > =A0CR .( Length of Assembler: ) . .( Bytes ) CR
>
> > > > > > What instruction is a CALL? =A0How do you specify the address? =
=A0How do
> > > > > > you specify literal data?
>
> > > > > > Rick
>
> > > > > $addr ,
>
> > > > How many bits are in an opcode, 4 or 5? =A0I would say it has to be=
 five
> > > > or there is no way for the machine to distinguish between an opcode
> > > > and an address. =A0In other words, there *has* to be a CALL instruc=
tion,
> > > > even if it is just a one bit opcode with the rest being the address=
.
>
> > > > Rick- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > if(instructionRegister<16) doOpcode(instructionRegister) else
> > > doSubroutine(instructionRegister);
>
> > > cheers jacko- Hide quoted text -
>
> > > - Show quoted text -
>
> > and how wide is instruction register?
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -
>
> Hi
>
> The instruction register width like all register widths are controlled
> by the generic parameter wide. if wide is 16 then 16 bit registers,
> datapaths, addressable element size, alu, instruction width, in fact
> all std_logic_vector of relavance are this generic width.
>
> So if the generic wide is set to 4096 then a 4096 bit microprocessor
> is rendered. Note the ALU will be slow until much if generate logic is
> written in the VHDL.
>
> As program and data memory address size is n bits and each addressable
> is n-bits, then memory size is n^2 bits.
>
> The useful knowledge of dividing the memory into optimized sections
> such as say the microcode section at 4 bits wide only, saves on bits,
> and means the instruction unpack logic is missing (no delays due to
> it), yet the same density is achived, well better!!
>
> This packing of the core 'microcode' to 4 bits is the main reason for
> not having literal fetch as one might expect.
>
> Then there is the next code layer, which is a threading list of
> subroutine addresses and possibly literal values. This can be
> compacted by using (m<n) m to n bit mapping, compression.
>
> Then you have a data space of n bit wide memory.
>
> Any other generics wanted??
>
> cheers jacko

oooo my god

so if you have 32 bit wide datapath
then you use 4 bits as instruction and WASTE 28 bits of the
instruction width?

this is soooo stupid, i could not take that option seriously in count,
that the reason why i asked how wide the instruction is!

Antti

Hi

> > The useful knowledge of dividing the memory into optimized sections
> > such as say the microcode section at 4 bits wide only, saves on bits,
> > and means the instruction unpack logic is missing (no delays due to
> > it), yet the same density is achived, well better!!
>
> > This packing of the core 'microcode' to 4 bits is the main reason for
> > not having literal fetch as one might expect.

0x000X in 4 bit memory 0xX

cheers jacko

hi

Chuck and the poe are in the design lab,

Chuck sys to pope "Have you got a rubber, my designs are getting big?"
Pope says "That's a bit RISCy!"

So if you had possiblly 4 instructions to do stack init pointers and
save both aswell, what would you use?

cheers jacko

In article <1478a4ab-62d3-4e9d-b1a3-769f847260a2@j8g2000yql.googlegroups.com>,
Jacko  <jackokring@gmail.com> wrote:
>hi
>
>Chuck and the poe are in the design lab,
>
>Chuck sys to pope "Have you got a rubber, my designs are getting big?"
>Pope says "That's a bit RISCy!"
>
>So if you had possiblly 4 instructions to do stack init pointers and
>save both aswell, what would you use?

Do you ever read over your posts before submission?
Do you have a spelling checker?

>
>cheers jacko


--
-- 
Albert van der Horst, UTRECHT,THE NETHERLANDS
Economic growth -- like all pyramid schemes -- ultimately falters.
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

On Mar 19, 11:08=A0pm, Albert van der Horst <alb...@spenarnc.xs4all.nl>
wrote:
> In article <1478a4ab-62d3-4e9d-b1a3-769f84726...@j8g2000yql.googlegroups.=
com>,
>
> Jacko =A0<jackokr...@gmail.com> wrote:
> >hi
>
> >Chuck and the poe are in the design lab,
>
> >Chuck sys to pope "Have you got a rubber, my designs are getting big?"
> >Pope says "That's a bit RISCy!"
>
> >So if you had possiblly 4 instructions to do stack init pointers and
> >save both aswell, what would you use?
>
> Do you ever read over your posts before submission?
> Do you have a spelling checker?


ROFLMAO!!! All the "stuff" this guy posts and you are commenting on
his ~~~spelling~~~!!!

Rick

On 20 Mar, 03:08, Albert van der Horst <alb...@spenarnc.xs4all.nl>
wrote:
> In article <1478a4ab-62d3-4e9d-b1a3-769f84726...@j8g2000yql.googlegroups.=
com>,
>
> Jacko =A0<jackokr...@gmail.com> wrote:
> >hi
>
> >Chuck and the poe are in the design lab,
>
> >Chuck sys to pope "Have you got a rubber, my designs are getting big?"
> >Pope says "That's a bit RISCy!"
>
> >So if you had possiblly 4 instructions to do stack init pointers and
> >save both aswell, what would you use?
>
> Do you ever read over your posts before submission?
> Do you have a spelling checker?
>
>
>
> >cheers jacko
>
> --
> --
> Albert van der Horst, UTRECHT,THE NETHERLANDS
> Economic growth -- like all pyramid schemes -- ultimately falters.
> albert@spe&ar&c.xs4all.nl &=3Dnhttp://home.hccnet.nl/a.w.m.van.der.horst

Darwin, Mutation and the Death of a Lnguage via Stagnation
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Oh yo evil looking mutated word, you is dead right, no sexy none. Me
bee's full oxford smili life, gets me the beer token and enduf this
wanton easo-speak.

cheers jacko