USB PHY

Started by March 25, 2009
Hi,

While searching for USB IP resources on the net I came across USB PHY
cores in verilog.


1) Why is it neessary to seperate USB controller and PHY in two
different cores? It may be necessary for 3.0 due to higher speeds but
what is the need for 1.1 and 2.0?
2) If USB PHY is a mixed (Analog & Digital) solution how can it be
offered only in verilog as developer claims?
How can a mixed core (GDSII and HDL) be implemented in FPGA?
3) If I have the USB and USB PHY cores seperately how do I implement
in FPGA and use/test it?


See the description of USB 1.1 PHY core from www.asics.ws. .


Thanks in advance.
br


***************************************************************************=
=AD
*****************************************************
"USB 1.1 PhyUSB 1.1 Physical Interface core. This core provides all
functions essential to interface to the USB 1.1 bus. This includes
serial/parallel conversion, bit stuffing and unstuffing, NRZI
encoding
and decoding and a DPLL. It comes with a industry standard UTMI
interface for easy portability


Sample Implementation Results
Technology Area Speed
Xilinx Spartan 2 xc2s50-6 111 LUTs (30%)  > 50 MHz


Currently this IP Core is available in Verilog only."
***************************************************************************=
=AD
*****************************************************
On Mar 25, 6:39=A0pm, bhavanire...@gmail.com wrote:
> Hi, > > While searching for USB IP resources on the net I came across USB PHY > cores in verilog. > > 1) Why is it neessary to seperate USB controller and PHY in two > different cores? It may be necessary for 3.0 due to higher speeds but > what is the need for 1.1 and 2.0? > 2) If USB PHY is a mixed (Analog & Digital) solution how can it be > offered only in verilog as developer claims? > How can a mixed core (GDSII and HDL) be implemented in FPGA? > 3) If I have the USB and USB PHY cores seperately how do I implement > in FPGA and use/test it? > > See the description of USB 1.1 PHY core fromwww.asics.ws. . > > Thanks in advance. > br > > *************************************************************************=
**=AD
> ***************************************************** > "USB 1.1 PhyUSB 1.1 Physical Interface core. This core provides all > functions essential to interface to the USB 1.1 bus. This includes > serial/parallel conversion, bit stuffing and unstuffing, NRZI > encoding > and decoding and a DPLL. It comes with a industry standard UTMI > interface for easy portability > > Sample Implementation Results > Technology Area Speed > Xilinx Spartan 2 xc2s50-6 111 LUTs (30%) =A0> 50 MHz > > Currently this IP Core is available in Verilog only." > *************************************************************************=
**=AD
> *****************************************************
those FPGA USB IP cores "PHY" are not the actual PHY actually the USB PHY can not be done with any FPGA reliable, only FPGA's with USB PHY are the CSSP stuff from QuickLogic what is referenced as USB PHY is the lower lever USB IP just before the actual PHY, that in that case the PHY is really a dumb tranceiver only there are hobby projects also where the USB pins are connected directly to FPGA also, but this possible violates some of the operationg specs. one such project used a special 1 bt soft core processor to perform usb host task (keyboard only) Antti
> what is referenced as USB PHY is the lower lever USB IP just before > the actual PHY, that in that case the PHY is really a dumb tranceiver > only
Thanks Antti. I will check QucikLogic stuff. In the aove case why can't that be part of USB controller core rather than a seperate core before PHY tranciever?
> there are hobby projects also where the USB pins are connected > directly > to FPGA also, but this possible violates some of the operationg specs. > one such project used a special 1 bt soft core processor to perform > usb host task (keyboard only)
OK.
> Antti- Hide quoted text - > > - Show quoted text -
On Wed, 25 Mar 2009 09:39:01 -0700 (PDT), bhavanireddy@gmail.com
wrote:

>Hi, > >While searching for USB IP resources on the net I came across USB PHY >cores in verilog. > > >1) Why is it neessary to seperate USB controller and PHY in two >different cores? It may be necessary for 3.0 due to higher speeds but >what is the need for 1.1 and 2.0?
The difference is the speed. USB 1.1 is 12 Mb/s and the "PHY" is basically three CMOS receivers (two single ended and one differential) and a tri-state CMOS drive so implementing the digital portion of the PHY in RTL is feasible. The analog portion of the PHY can be implemented by the standard IOs one can find on an FPGA in most cases even though it may not be fully compliant. USB 2.0 (at least high speed portion thereof) is 480 Mb/s and need special IO for both receiver and transmitter and this IO doesn't exist on any FPGA I know of. Also there are quite challenging clock recovery requirements which make even implementation of the "digital" portion of the PHY challenging. Interestingly USB 3.0 is quite similar to PCI Express and we may see full implementations in FPGAs. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
On Mar 25, 8:15=A0pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Wed, 25 Mar 2009 09:39:01 -0700 (PDT), bhavanire...@gmail.com > wrote: > > >Hi, > > >While searching for USB IP resources on the net I came across USB PHY > >cores in verilog. > > >1) Why is it neessary to seperate USB controller and PHY in two > >different cores? It may be necessary for 3.0 due to higher speeds but > >what is the need for 1.1 and 2.0? > > The difference is the speed. USB 1.1 is 12 Mb/s and the "PHY" is > basically three CMOS receivers (two single ended and one differential) > and a tri-state CMOS drive so implementing the digital portion of the > PHY in RTL is feasible. The analog portion of the PHY can be > implemented by the standard IOs one can find on an FPGA in most cases > even though it may not be fully compliant. > USB 2.0 (at least =A0high speed portion thereof) is 480 Mb/s and need > special IO for both receiver and transmitter and this IO doesn't exist > on any FPGA I know of. Also there are quite challenging clock recovery > requirements which make even implementation of the "digital" portion > of the PHY challenging. > Interestingly USB 3.0 is quite similar to PCI Express and we may see > full implementations in FPGAs. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.com
Virtex-5 is fully USB-3 compliant, PLDA had live demo on EW2009 Antti
On Mar 25, 2:18=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Mar 25, 8:15=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > > On Wed, 25 Mar 2009 09:39:01 -0700 (PDT), bhavanire...@gmail.com > > wrote: > > > >Hi, > > > >While searching for USB IP resources on the net I came across USB PHY > > >cores in verilog. > > > >1) Why is it neessary to seperate USB controller and PHY in two > > >different cores? It may be necessary for 3.0 due to higher speeds but > > >what is the need for 1.1 and 2.0? > > > The difference is the speed. USB 1.1 is 12 Mb/s and the "PHY" is > > basically three CMOS receivers (two single ended and one differential) > > and a tri-state CMOS drive so implementing the digital portion of the > > PHY in RTL is feasible. The analog portion of the PHY can be > > implemented by the standard IOs one can find on an FPGA in most cases > > even though it may not be fully compliant. > > USB 2.0 (at least =A0high speed portion thereof) is 480 Mb/s and need > > special IO for both receiver and transmitter and this IO doesn't exist > > on any FPGA I know of. Also there are quite challenging clock recovery > > requirements which make even implementation of the "digital" portion > > of the PHY challenging. > > Interestingly USB 3.0 is quite similar to PCI Express and we may see > > full implementations in FPGAs. > > -- > > Muzaffer Kal > > > DSPIA INC. > > ASIC/FPGA Design Serviceshttp://www.dspia.com > > Virtex-5 is fully USB-3 compliant, PLDA had live demo > on EW2009 > > Antti- Hide quoted text - > > - Show quoted text -
What about Virtex 4FX? Is it fully USB-3 compiant?
On Mar 26, 12:29=A0am, leevv <le...@mail.ru> wrote:
> On Mar 25, 2:18=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Mar 25, 8:15=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > On Wed, 25 Mar 2009 09:39:01 -0700 (PDT), bhavanire...@gmail.com > > > wrote: > > > > >Hi, > > > > >While searching for USB IP resources on the net I came across USB PH=
Y
> > > >cores in verilog. > > > > >1) Why is it neessary to seperate USB controller and PHY in two > > > >different cores? It may be necessary for 3.0 due to higher speeds bu=
t
> > > >what is the need for 1.1 and 2.0? > > > > The difference is the speed. USB 1.1 is 12 Mb/s and the "PHY" is > > > basically three CMOS receivers (two single ended and one differential=
)
> > > and a tri-state CMOS drive so implementing the digital portion of the > > > PHY in RTL is feasible. The analog portion of the PHY can be > > > implemented by the standard IOs one can find on an FPGA in most cases > > > even though it may not be fully compliant. > > > USB 2.0 (at least =A0high speed portion thereof) is 480 Mb/s and need > > > special IO for both receiver and transmitter and this IO doesn't exis=
t
> > > on any FPGA I know of. Also there are quite challenging clock recover=
y
> > > requirements which make even implementation of the "digital" portion > > > of the PHY challenging. > > > Interestingly USB 3.0 is quite similar to PCI Express and we may see > > > full implementations in FPGAs. > > > -- > > > Muzaffer Kal > > > > DSPIA INC. > > > ASIC/FPGA Design Serviceshttp://www.dspia.com > > > Virtex-5 is fully USB-3 compliant, PLDA had live demo > > on EW2009 > > > Antti- Hide quoted text - > > > - Show quoted text - > > What about Virtex 4FX? Is it fully USB-3 compiant?
no