virtex-5 lvds termination issue?

Hi,
I've been working on a high speed ADC board which has a LVDS outputs
connected to a virtex-5 lx 50. The ADC board has 100 ohm differential
lines but no receiver termination so I configured the IOs on the FPGA
side to be LVDS_25 with DIFF_TERM option on. I connected the ADC board
to the FPGA board and did a capture with a chipscope block and the
data was what we'd expect. The problem started after we replaced the
-1 speed V5 with a -3 speed chip on the FPGA board. The captured data
changed significantly and even changing the sampling points on the
FPGA didn't help at all. 
I looked at the ADC/FPGA interface with a DSO and there are large
over/undershoots which seem to be caused by significant reflections.
Initially I thought this could be the result of the FPGA replacement
but I had the board x-ray'ed and there seems to be no alignment or
ball short problems. Also everything else seems to work as before on
the board so now the suspicion is more towards the on chip termination
of the FPGA not being quite right. 
Does anyone have any experience with Virtex-5 on-chip lvds
termination? Is there anything we can do to play with the value of the
termination resistor? I'm assuming these are calibrated termination
resistors, so maybe we can get some access to the calibration
circuitry and see if we can find a value which works better for us?
Obviously turning of the diff_term makes the result significantly
worse so it maybe just that the value is not right at a high speed
chip for some reason. I'd appreciate any comments/suggestions.

Thanks.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Muzaffer Kal wrote:
> Does anyone have any experience with Virtex-5 on-chip lvds
> termination? Is there anything we can do to play with the value of the
> termination resistor? I'm assuming these are calibrated termination
> resistors, so maybe we can get some access to the calibration
> circuitry and see if we can find a value which works better for us?
> Obviously turning of the diff_term makes the result significantly
> worse so it maybe just that the value is not right at a high speed
> chip for some reason. I'd appreciate any comments/suggestions.

Not sure if this helps you any, but I had a similar problem with Virtex4.
As it turns out, the differential termination givs you 100 Ohms only if
the VCCO of the bank the IO is in is 2.5V, anything else will give you
"unspecified" values for the termination. That I overlooked designing
the board, because I figured the LVDS input buffers are powered by
VCCAUX, which is 2.5V in all cases, so it doesn't really matter what
VCCO is.

You can put LVDS inputs in all banks regardless of their VCCO, but the
differential termination will then be off. When I was designing the
board, this was a footnote in some table in the data sheet, in the
meantime it's been moved to the text somewhere.

Don't know if it's still the same in Virtex5.

HTH,
Sean

-- 
Replace MONTH with the three-letter-abbreviation for the current
month. Simple, eh?

Which ADC?
Sampling rate?
How did you probe the signals with your DSO?
What DSO?
What 'scope probe?
In what way did the captured data change?
How did you change the FPGA sampling points?

Syms. 

On Thu, 26 Mar 2009 11:15:41 -0000, "Symon" <symon_brewer@hotmail.com>
wrote:

>Which ADC?
>Sampling rate?
>How did you probe the signals with your DSO?
>What DSO?
>What 'scope probe?
>In what way did the captured data change?
>How did you change the FPGA sampling points?
>
>Syms. 
>
I'm using an AD9480 at 250 MHz supplied by V5 using an LVPECL output.
For my purposes the quality of the output clock from the fpga is
adequate. The DSO is an Agilent rental with a whole set of probes and
I looked at the ADC outputs with both a single ended probe and an
active differential probe with 91 ohm termination. 
The data I observed on the board has significant over/undershoots and
the captured data shows the same. I'm using a slew controlled pulse
driver at the input (coming differentially through a transformer) of
the ADC and I'm seeing bumps and dips in the captured data at the
locations where there are over/undershoots on the line as expected.
In the fpga I have a PLL which receives the clock output from the ADC
and generates clock for my internal logic. I generated another output
from the PLL which has 4 swept phases (ie 0, pi/2, pi and 3pi/2
delays) from the incoming clock and used it to capture the incoming
data. If it were a sampling time issue, one of the phases would be
good to sample.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

"Muzaffer Kal" <kal@dspia.com> wrote in message 
news:pe3ns4djft0dbsniu2223snu8cmfisc04j@4ax.com...

> I'm using an AD9480 at 250 MHz supplied by V5 using an LVPECL output.
> For my purposes the quality of the output clock from the fpga is
> adequate. The DSO is an Agilent rental with a whole set of probes and
> I looked at the ADC outputs with both a single ended probe and an
> active differential probe with 91 ohm termination.
> The data I observed on the board has significant over/undershoots and
> the captured data shows the same. I'm using a slew controlled pulse
> driver at the input (coming differentially through a transformer) of
> the ADC and I'm seeing bumps and dips in the captured data at the
> locations where there are over/undershoots on the line as expected.
> In the fpga I have a PLL which receives the clock output from the ADC
> and generates clock for my internal logic. I generated another output
> from the PLL which has 4 swept phases (ie 0, pi/2, pi and 3pi/2
> delays) from the incoming clock and used it to capture the incoming
> data. If it were a sampling time issue, one of the phases would be
> good to sample.
>
The ADC has high impedance current source outputs, so the LVDS termination 
in the FPGA is important. However, I've always found the DIFF_TERM to be 
just fine. Is your ADC close to the FPGA?

I can't quite work out from your posts what you are looking at with the DSO. 
Sometimes it seems you are referring to the analog input signal, and other 
times the LVDS signals from the ADC to the FPGA. Perhaps you can clarify 
that. FWIW it's very hard to probe high speed LVDS differential signals. 
Looking at the source pins won't give a nice 'scope picture. Much better is 
to use a simulator like HyperLynx to work out what's going on.
Are you saying that the overshoots you see on the LVDS lines are somehow 
being coupled to the analog signal? I hope you haven't split your ground 
plane into analog and digital sections.

HTH, Syms. 

One more thing, did you terminate the clock signal at the ADC clock 
receiver? The ADC doesn't have on board termination from what I see on the 
datasheet. 

>
> I looked at the ADC/FPGA interface with a DSO and there are large
> over/undershoots which seem to be caused by significant reflections.
>

 Some past posts that might be useful, regarding the use of
other high speed LVDS A/D's lacking driver back termination :

 http://groups.google.com/group/comp.arch.fpga/msg/85db6dc0bca5c0da
 http://groups.google.com/group/comp.arch.fpga/msg/95809af82ccbb550
 http://groups.google.com/group/comp.arch.fpga/msg/5a8720eec942612e

 The pdf files referenced in the above posts have now moved here:

 http://fpgastuff.googlepages.com/oldaolfiles

 ( Last fall, AOL silently axed the ftp space where I'd been
stashing examples for the past decade )

Brian