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Using LVDS in Lattice ECP3

Started by PGS March 27, 2009
We need a quick guide about how to instantiate a LVDS input and a LVDS
output on the ECP3.

Using the VHDL language (and Symplicity), we would like to use a set
of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA).
I would expect, that I could instantiate a LVDS-input-cell by naming
two input ports and providing their proper "LOC" attribute (say again
for AN and AP), and then use AQ for the single-ended buffer output
connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should
IO_TYPE attribute be applied to LVDS cells ?
Similar arrangement for output.
Is this correct ? Or is there another way ?
What is the name of the LVDS25_IN and LVDS25_OUT cells ?
Thanks !
On Mar 27, 4:46=A0pm, PGS <p...@algonordic.dk> wrote:
> We need a quick guide about how to instantiate a LVDS input and a LVDS > output on the ECP3. > > Using the VHDL language (and Symplicity), we would like to use a set > of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). > I would expect, that I could instantiate a LVDS-input-cell by naming > two input ports and providing their proper "LOC" attribute (say again > for AN and AP), and then use AQ for the single-ended buffer output > connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should > IO_TYPE attribute be applied to LVDS cells ? > Similar arrangement for output. > Is this correct ? Or is there another way ? > What is the name of the LVDS25_IN and LVDS25_OUT cells ? > Thanks !
RTFM :) if i recall correctly if you constrain the positive pad and select some LVDS io standard the rest is done by the lattice tools but you just need to read the docs and try out Antti
On Mar 27, 11:18=A0am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Mar 27, 4:46=A0pm, PGS <p...@algonordic.dk> wrote: > > > We need a quick guide about how to instantiate a LVDS input and a LVDS > > output on the ECP3. > > > Using the VHDL language (and Symplicity), we would like to use a set > > of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). > > I would expect, that I could instantiate a LVDS-input-cell by naming > > two input ports and providing their proper "LOC" attribute (say again > > for AN and AP), and then use AQ for the single-ended buffer output > > connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should > > IO_TYPE attribute be applied to LVDS cells ? > > Similar arrangement for output. > > Is this correct ? Or is there another way ? > > What is the name of the LVDS25_IN and LVDS25_OUT cells ? > > Thanks ! > > RTFM :) > > if i recall correctly if you constrain the positive pad and select > some LVDS io standard the rest is done by the lattice tools > but you just need to read the docs and try out > > Antti
That was true for the tools I use, so no reason they would change for ECP3. Basically pretend the world is single-ended and the negative side of your differential pairs is inferred by the I/O standard. Locating both pins is redundant because there is only one possible I/O pairing. Just make sure you reserve the negative pins...
On Mar 27, 11:27=A0am, gabor <ga...@alacron.com> wrote:
> On Mar 27, 11:18=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Mar 27, 4:46=A0pm, PGS <p...@algonordic.dk> wrote: > > > > We need a quick guide about how to instantiate a LVDS input and a LVD=
S
> > > output on the ECP3. > > > > Using the VHDL language (and Symplicity), we would like to use a set > > > of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). > > > I would expect, that I could instantiate a LVDS-input-cell by naming > > > two input ports and providing their proper "LOC" attribute (say again > > > for AN and AP), and then use AQ for the single-ended buffer output > > > connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should > > > IO_TYPE attribute be applied to LVDS cells ? > > > Similar arrangement for output. > > > Is this correct ? Or is there another way ? > > > What is the name of the LVDS25_IN and LVDS25_OUT cells ? > > > Thanks ! > > > RTFM :) > > > if i recall correctly if you constrain the positive pad and select > > some LVDS io standard the rest is done by the lattice tools > > but you just need to read the docs and try out > > > Antti > > That was true for the tools I use, so no reason they would change > for ECP3. =A0Basically pretend the world is single-ended and the > negative side of your differential pairs is inferred by the > I/O standard. =A0Locating both pins is redundant because there > is only one possible I/O pairing. =A0Just make sure you reserve > the negative pins...
Oops, didn't see the other questions... The LVDS I/O standard is called LVDS25 (at least for ECP and ECP2). The easiest way to set your IO standards is using the spreadsheet view in the Design Planner (Pre-Map). In the IO Standard column you can right click an item and get a drop-down list of choices. Regards, Gabor