DCM vs PLL

Hi,

From the datasheets, it is looks like the only major difference
between DCM and PLL is that PLL additionally does jitter filtering.
Rest of the features are present in both these macros. So what decides
whether one should use a PLL or DCM in FPGA.

The following are the common features present in both DCM and PLL:
1) frequency synth
2) deskew
3) frequency div

Additionally DCM can also do phase shift.

Regards,
Sharan

On 1 Apr., 16:01, Sharan <sharan.basa...@gmail.com> wrote:
> Hi,
>
> From the datasheets, it is looks like the only major difference
> between DCM and PLL is that PLL additionally does jitter filtering.
> Rest of the features are present in both these macros. So what decides
> whether one should use a PLL or DCM in FPGA.
>
> The following are the common features present in both DCM and PLL:
> 1) frequency synth
> 2) deskew
> 3) frequency div
>
> Additionally DCM can also do phase shift.

PLL's do that too.

DCM's have a higher potential for failures due tu their state-machine
behaviour.

For Example EMI could disturb some clocks getting into a DCM locking
up and you need a systen reset.

Analog PLL's are more tolerant about that and especially if you want
to have deterministic jitter-fitering you are lost with the DCM.

I would always chose a good analog PLL over DCM.

"Sharan" <sharan.basappa@gmail.com> wrote in message 
news:6374ea0e-4cdb-474a-9cd6-df68f8252302@v15g2000yqn.googlegroups.com...
> Hi,
>
> From the datasheets, it is looks like the only major difference
> between DCM and PLL is that PLL additionally does jitter filtering.
> Rest of the features are present in both these macros. So what decides
> whether one should use a PLL or DCM in FPGA.
>
> The following are the common features present in both DCM and PLL:
> 1) frequency synth
> 2) deskew
> 3) frequency div
>
> Additionally DCM can also do phase shift.
>
> Regards,
> Sharan

PLL's have a higher potential for failures due tu their non-state-machine
behaviour.

For Example EMI could disturb some clocks getting into a PLL phase
detector and you get a lock loss.

Digital DCM's are more tolerant about that and especially if you want
to have deterministic operation that is not component value dependent you 
are lost with the PLL.

I would always chose a good DCM over analog PLL. 

"Symon" <symon_brewer@hotmail.com> wrote:

>
>"Sharan" <sharan.basappa@gmail.com> wrote in message 
>news:6374ea0e-4cdb-474a-9cd6-df68f8252302@v15g2000yqn.googlegroups.com...
>> Hi,
>>
>> From the datasheets, it is looks like the only major difference
>> between DCM and PLL is that PLL additionally does jitter filtering.
>> Rest of the features are present in both these macros. So what decides
>> whether one should use a PLL or DCM in FPGA.
>>
>> The following are the common features present in both DCM and PLL:
>> 1) frequency synth
>> 2) deskew
>> 3) frequency div
>>
>> Additionally DCM can also do phase shift.
>>
>> Regards,
>> Sharan
>
>PLL's have a higher potential for failures due tu their non-state-machine
>behaviour.
>
>For Example EMI could disturb some clocks getting into a PLL phase
>detector and you get a lock loss.
>
>Digital DCM's are more tolerant about that and especially if you want
>to have deterministic operation that is not component value dependent you 
>are lost with the PLL.
>
>I would always chose a good DCM over analog PLL. 

Now I'm confused :-)


-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

Sharan,

The DCM requires less area in silicon, thus we can provide more of
them.

They are digital, and greatly immune to power supply noise (as
compared to PLL's).

They are a state machine, so a "crummy clock" signal is NOT
recommended, as a DCM will have a hard time, where  a PLL is commonly
used to "clean up" a "crummy clock" in order to make it useful at all.

DCM will add totally random, white, broad band jitter, where a PLL
will remove high frequency jitter, while adding low frequency jitter
(due to its oscillator having very low Q on the silicon).  It will
also add as jitter any power supply noise present varies the VCO in
the PLL.

External PLL's may be used with voltage controlled crystal oscillators
where the quality of the on-chip PLL oscillator is unacceptable (for
example SONET/SDH transmit clock jitter requirements are tough to meet
without a very high Q resonantor).

PLL and DCM have their uses.  We provide a mix of both, and you may
precede a DCM with a PLL if you have a "crummy clock" or pass the DCM
through the PLL if you wish to remove all nearly all the high
frequency jitter components.

The DCM also offers precise dynamic phase shifting, which is not so
easy to do in a PLL.

Use a hammer for nails, and a screwdriver for screws.  They are both
fasteners.  Which is better?  Silly question.

Austin

On 1 Apr., 17:36, "Symon" <symon_bre...@hotmail.com> wrote:
> PLL's have a higher potential for failures due tu their non-state-machine
> behaviour.
>
> For Example EMI could disturb some clocks getting into a PLL phase
> detector and you get a lock loss.

Did i miss some braindead engineer's pll design which needs a reset
after it got out of lock like the DCM's i know?

> Digital DCM's are more tolerant about that and especially if you want
> to have deterministic operation that is not component value dependent you
> are lost with the PLL.

And i also seem to have missed analog PLLs in FPGA's whose process
temperature voltage variations violate the specs.

> I would always chose a good DCM over analog PLL.- Zitierten Text ausblenden -

That's good as long as you can forbid your devices to pick up EMI or
any noise on it's clocks and do a preventive restart every minute or
so.

On Apr 1, 10:36=A0am, "Symon" <symon_bre...@hotmail.com> wrote:
> "Sharan" <sharan.basa...@gmail.com> wrote in message
>
> news:6374ea0e-4cdb-474a-9cd6-df68f8252302@v15g2000yqn.googlegroups.com...
>
>
>
>
>
> > Hi,
>
> > From the datasheets, it is looks like the only major difference
> > between DCM and PLL is that PLL additionally does jitter filtering.
> > Rest of the features are present in both these macros. So what decides
> > whether one should use a PLL or DCM in FPGA.
>
> > The following are the common features present in both DCM and PLL:
> > 1) frequency synth
> > 2) deskew
> > 3) frequency div
>
> > Additionally DCM can also do phase shift.
>
> > Regards,
> > Sharan
>
> PLL's have a higher potential for failures due tu their non-state-machine
> behaviour.
>
> For Example EMI could disturb some clocks getting into a PLL phase
> detector and you get a lock loss.
>
> Digital DCM's are more tolerant about that and especially if you want
> to have deterministic operation that is not component value dependent you
> are lost with the PLL.
>
> I would always chose a good DCM over analog PLL.- Hide quoted text -
>
> - Show quoted text -

Haha, It rings the bell about the battle between DLL vs. PLL not long
ago. :-)

So far, jitter is the only thing I concern about... so who's the
winner ?

<filter001@desinformation.de> wrote in message 
news:ec6505f4-7051-48e8-b471-6bd5849ded65@q16g2000yqg.googlegroups.com...
> On 1 Apr., 16:01, Sharan <sharan.basa...@gmail.com> wrote:
> DCM's have a higher potential for failures due tu their state-machine
> behaviour.
>
> For Example EMI could disturb some clocks getting into a DCM locking
> up and you need a systen reset.

Did i miss some braindead engineer's DCM design which has terrible stability 
causing it to get out of lock like the PLL's i know?

> Analog PLL's are more tolerant about that and especially if you want
> to have deterministic jitter-fitering you are lost with the DCM.

And i also seem to have missed DCMs in FPGA's whose jitter performance 
violate the specs.

> I would always chose a good analog PLL over DCM.- Zitierten Text 
> ausblenden -

That's good as long as you can forbid your devices to pick up EMI or
any noise on it's clocks and constantly check the phase lock. 

On Wed, 1 Apr 2009 13:26:47 -0700 (PDT)
halong <ccon67@netscape.net> wrote:

> On Apr 1, 10:36=A0am, "Symon" <symon_bre...@hotmail.com> wrote:
> > "Sharan" <sharan.basa...@gmail.com> wrote in message
> >
> > news:6374ea0e-4cdb-474a-9cd6-df68f8252302@v15g2000yqn.googlegroups.com.=
..
> >
> >
> >
> >
> >
> > > Hi,
> >
> > > From the datasheets, it is looks like the only major difference
> > > between DCM and PLL is that PLL additionally does jitter
> > > filtering. Rest of the features are present in both these macros.
> > > So what decides whether one should use a PLL or DCM in FPGA.
> >
> > > The following are the common features present in both DCM and PLL:
> > > 1) frequency synth
> > > 2) deskew
> > > 3) frequency div
> >
> > > Additionally DCM can also do phase shift.
> >
> > > Regards,
> > > Sharan
> >
> > PLL's have a higher potential for failures due tu their
> > non-state-machine behaviour.
> >
> > For Example EMI could disturb some clocks getting into a PLL phase
> > detector and you get a lock loss.
> >
> > Digital DCM's are more tolerant about that and especially if you
> > want to have deterministic operation that is not component value
> > dependent you are lost with the PLL.
> >
> > I would always chose a good DCM over analog PLL.- Hide quoted text -
> >
> > - Show quoted text -
>=20
> Haha, It rings the bell about the battle between DLL vs. PLL not long
> ago. :-)
>=20
> So far, jitter is the only thing I concern about... so who's the
> winner ?
>=20

DCM shows.  PLL places.  Starting off with a good crystal oscillator in
first place wins by a length.

--=20
Rob Gaddi, Highland Technology
Email address is currently out of order