Forums

delays in XC95144XL CPLD

Started by David Fejes April 2, 2009
Hello,

I want to use the XC95144XL CPLD to switching paralell video buses up
to 165Mhz frequency. The logic has only combinatorial parts and there
are no feedbacks from the macrocells output to the FastConnectII
inputs.
It's very important that the signals must have the same delays but I'm
a bit confused with the delays and the timing modells.

I don't use registers or any feedback in my configuration, so I'm
pretty sure that Fsystem is irrelevant to me. The combinatorial delays
are given as Tpdi for different speed grades, but I'm not sure wether
this delay is uniform or not. My Pterms have the same configurations
in all FBs due to the symmetrical topology.

Will it work with a 10 (lowest) speed grade CPLD or not? Shall I use a
faster (and a much more expensive) version or not? What will be the
order of jitters between the paralell signals?

Thank you for the answers
David

PS: timings are available at http://www.xilinx.com/support/documentation/data_sheets/ds056.pdf
p5-p6
On Apr 2, 11:12=A0am, David Fejes <fej...@gmail.com> wrote:
> Hello, > > I want to use the XC95144XL CPLD to switching paralell video buses up > to 165Mhz frequency. The logic has only combinatorial parts and there > are no feedbacks from the macrocells output to the FastConnectII > inputs. > It's very important that the signals must have the same delays but I'm > a bit confused with the delays and the timing modells. > > I don't use registers or any feedback in my configuration, so I'm > pretty sure that Fsystem is irrelevant to me. The combinatorial delays > are given as Tpdi for different speed grades, but I'm not sure wether > this delay is uniform or not. My Pterms have the same configurations > in all FBs due to the symmetrical topology. > > Will it work with a 10 (lowest) speed grade CPLD or not? Shall I use a > faster (and a much more expensive) version or not? What will be the > order of jitters between the paralell signals? > > Thank you for the answers > David > > PS: timings are available athttp://www.xilinx.com/support/documentation/d=
ata_sheets/ds056.pdf
> p5-p6
have you looked the CPLD output signals at 165MHz with a good DSO? I have. For a project where it was important to generate 120mhz phase shifted clocks with an CPLD. as much as i recall i did not like the cpld output waveforms what i observed. running parallel 165mhz datapaths via XC95 doesnt sound like a good idea but maybe i am wrong, has happened b4 Antti
> running parallel 165mhz datapaths via XC95 doesnt sound like a good > idea > but maybe i am wrong, has happened b4
There is a similar application note at the Xilinx webpage in the xapp944.pdf It is true that the maximum frequency of the signals is only 27Mhz in this design and it uses CoolRunnerII instead of XC95, but there is a interesting sentence at the end of the document: ,,All similar signals travel through the same path in the CPLD, so they will emerge from the other side with negligible skew, because of to the deterministic nature of the timing model and architecture." I think it should be true at higher frequencies too, didn't? On Apr 2, 10:18=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:
> On Apr 2, 11:12=A0am, David Fejes <fej...@gmail.com> wrote: > > > > > Hello, > > > I want to use the XC95144XL CPLD to switching paralell video buses up > > to 165Mhz frequency. The logic has only combinatorial parts and there > > are no feedbacks from the macrocells output to the FastConnectII > > inputs. > > It's very important that the signals must have the same delays but I'm > > a bit confused with the delays and the timing modells. > > > I don't use registers or any feedback in my configuration, so I'm > > pretty sure that Fsystem is irrelevant to me. The combinatorial delays > > are given as Tpdi for different speed grades, but I'm not sure wether > > this delay is uniform or not. My Pterms have the same configurations > > in all FBs due to the symmetrical topology. > > > Will it work with a 10 (lowest) speed grade CPLD or not? Shall I use a > > faster (and a much more expensive) version or not? What will be the > > order of jitters between the paralell signals? > > > Thank you for the answers > > David > > > PS: timings are available athttp://www.xilinx.com/support/documentation=
/data_sheets/ds056.pdf
> > p5-p6 > > have you looked the CPLD output signals at 165MHz with a good DSO? > I have. For a project where it was important to generate 120mhz phase > shifted > clocks with an CPLD. as much as i recall i did not like the cpld > output > waveforms what i observed. > > running parallel 165mhz datapaths via XC95 doesnt sound like a good > idea > but maybe i am wrong, has happened b4 > > Antti
On Apr 2, 6:01=A0am, David Fejes <fej...@gmail.com> wrote:
> > running parallel 165mhz datapaths via XC95 doesnt sound like a good > > idea > > but maybe i am wrong, has happened b4 > > There is a similar application note at the Xilinx webpage in the > xapp944.pdf =A0It is true that the maximum frequency of the signals is > only 27Mhz in this design and it uses CoolRunnerII instead of XC95, > but there is a interesting sentence at the end of the document: > > ,,All similar signals travel through the same path in the CPLD, so > they will emerge from the other side with negligible skew, because of > to the deterministic nature of the timing model and architecture." > > I think it should be true at higher frequencies too, didn't? > > On Apr 2, 10:18=A0am, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 2, 11:12=A0am, David Fejes <fej...@gmail.com> wrote: > > > > Hello, > > > > I want to use the XC95144XL CPLD to switching paralell video buses up > > > to 165Mhz frequency. The logic has only combinatorial parts and there > > > are no feedbacks from the macrocells output to the FastConnectII > > > inputs. > > > It's very important that the signals must have the same delays but I'=
m
> > > a bit confused with the delays and the timing modells. > > > > I don't use registers or any feedback in my configuration, so I'm > > > pretty sure that Fsystem is irrelevant to me. The combinatorial delay=
s
> > > are given as Tpdi for different speed grades, but I'm not sure wether > > > this delay is uniform or not. My Pterms have the same configurations > > > in all FBs due to the symmetrical topology. > > > > Will it work with a 10 (lowest) speed grade CPLD or not? Shall I use =
a
> > > faster (and a much more expensive) version or not? What will be the > > > order of jitters between the paralell signals? > > > > Thank you for the answers > > > David > > > > PS: timings are available athttp://www.xilinx.com/support/documentati=
on/data_sheets/ds056.pdf
> > > p5-p6 > > > have you looked the CPLD output signals at 165MHz with a good DSO? > > I have. For a project where it was important to generate 120mhz phase > > shifted > > clocks with an CPLD. as much as i recall i did not like the cpld > > output > > waveforms what i observed. > > > running parallel 165mhz datapaths via XC95 doesnt sound like a good > > idea > > but maybe i am wrong, has happened b4 > > > Antti > >
You may find that the skew is not your problem, but the switching capability of the output drivers in the XC9500 series. Fmax is not just because of clocks, slow output drivers may have reduced output swing and unacceptable rise and fall times at 165 MHz.
On Apr 2, 10:01=A0pm, David Fejes <fej...@gmail.com> wrote:
> > running parallel 165mhz datapaths via XC95 doesnt sound like a good > > idea > > but maybe i am wrong, has happened b4 > > There is a similar application note at the Xilinx webpage in the > xapp944.pdf =A0It is true that the maximum frequency of the signals is > only 27Mhz in this design and it uses CoolRunnerII instead of XC95, > but there is a interesting sentence at the end of the document: > > ,,All similar signals travel through the same path in the CPLD, so > they will emerge from the other side with negligible skew, because of > to the deterministic nature of the timing model and architecture." > > I think it should be true at higher frequencies too, didn't?
What load is this driving, and what time variance can you tolerate ? Within the CPLD the data paths are nominally the same, but you will find signals further from GND pins are more variable, and the signals will also have different thermal-delay-profiles. It's normally best to have the device delays a fraction of our signal, so any variations in those delays are an even smaller fraction of your signal. Why chose the XC95xxx ? -jg
On Apr 2, 11:27=A0pm, -jg <Jim.Granvi...@gmail.com> wrote:
> On Apr 2, 10:01=A0pm, David Fejes <fej...@gmail.com> wrote: > > > > running parallel 165mhz datapaths via XC95 doesnt sound like a good > > > idea > > > but maybe i am wrong, has happened b4 > > > There is a similar application note at the Xilinx webpage in the > > xapp944.pdf =A0It is true that the maximum frequency of the signals is > > only 27Mhz in this design and it uses CoolRunnerII instead of XC95, > > but there is a interesting sentence at the end of the document: > > > ,,All similar signals travel through the same path in the CPLD, so > > they will emerge from the other side with negligible skew, because of > > to the deterministic nature of the timing model and architecture." > > > I think it should be true at higher frequencies too, didn't? > > What load is this driving, and what time variance can you tolerate ?
The time variance should be less than 1ns. Only one IC is connected to the outputs.
> Within the CPLD the data paths are nominally the same, but you will > find signals further from GND pins are more variable, and the signals > will also have different thermal-delay-profiles. > It's normally best to have the device delays a fraction of our signal, > so > any variations in those delays are an even smaller fraction of your > signal. > > Why chose the XC95xxx ?
There was three main reason: - high IO count with relative low cost - FBs have 54 inputs, it gives more freedoom at mapping output pins (Coolrunner II FBs have only 40) - FastConnectII provides uniform delay so inputs can be mapped freely... Can you offer a better solution? BTW, I have just examined a CoolRunnerII X-Board (a Digilent devboard) and I have measured 120ns rise time on the outputs. I don't understand, maybe I made mistake somewhere.. (the datasheet specifies 4.5ns....) David
David Fejes <fejesd@gmail.com> writes:

>Can you offer a better solution?
If you don't need to multiplex the signals at 160MHz, what about Quickswitch? http://www.idt.com/?catID=58731&loc=1&bHt=961 -- Georg Acher, acher@in.tum.de http://www.lrr.in.tum.de/~acher "Oh no, not again !" The bowl of petunias
On Apr 3, 9:51=A0pm, David Fejes <fej...@gmail.com> wrote:
> Can you offer a better solution?
You should be able to target both Xilinx CPLD families easily and see what the timing reports say. How many pins are switched on this, and how wide are the busses. I'd expect the newer CR2 devices to have better 165MHz performance, and you may need certain packages, if a lot of lines are active. Ask XiIinx.
> > BTW, I have just examined a CoolRunnerII X-Board (a Digilent devboard) > and I have measured 120ns rise time on the outputs. I don't > understand, maybe I made mistake somewhere.. (the datasheet specifies > 4.5ns....)
Sounds like your measuring bandwidth is rather low. -jg
On Apr 3, 6:17=A0am, -jg <Jim.Granvi...@gmail.com> wrote:
> On Apr 3, 9:51=A0pm, David Fejes <fej...@gmail.com> wrote: > > > Can you offer a better solution? > > You should be able to target both Xilinx CPLD families easily and see > what the timing > reports say. > > How many pins are switched on this, and how wide are the busses. > > I'd expect the newer CR2 devices to have better 165MHz performance, > and you may need certain packages, if a lot of lines are active. > Ask XiIinx. > > > > > BTW, I have just examined a CoolRunnerII X-Board (a Digilent devboard) > > and I have measured 120ns rise time on the outputs. I don't > > understand, maybe I made mistake somewhere.. (the datasheet specifies > > 4.5ns....) > > Sounds like your measuring bandwidth is rather low. > > -jg
Is the output set to open-drain?