clock multipliers, dividers, and more clocks...

Ok,

so I have a system that has a 25mhz clock built on it, and I'd like to
have either a 20mhz clock or a 100mhz clock,

Now I'm thinking of options,

1) make a 20mhz clock out of the 25mhz.
- the obvious idea is to count up to 5 and force a state change on one
of the counts, but this will give me a 80/20 duty cycle. If i'm only
clocking on the rising edge, is this a problem?

2) how would I make a 20mhz clock out of the 25mhz with a closer to
50/50 duty cycle?

3) I keep hearing about clock mulitpliers, how is that done in an
fpga?  I could on paper multiply the 25mhz by 4 and have a 100mhz
clock, that would be good...

4) given I have input pins on my fpga, could I make up a daughter
card, that has a 100mhz oscillator on it, send that signal in on one
of the pins and use that as the clock and ignore the 25mhz clock?


Tia,

Jonathan

On Apr 2, 3:46=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
> Ok,
>
> so I have a system that has a 25mhz clock built on it, and I'd like to
> have either a 20mhz clock or a 100mhz clock,
>
> Now I'm thinking of options,
>
> 1) make a 20mhz clock out of the 25mhz.
> - the obvious idea is to count up to 5 and force a state change on one
> of the counts, but this will give me a 80/20 duty cycle. If i'm only
> clocking on the rising edge, is this a problem?
>
> 2) how would I make a 20mhz clock out of the 25mhz with a closer to
> 50/50 duty cycle?
>
> 3) I keep hearing about clock mulitpliers, how is that done in an
> fpga? =A0I could on paper multiply the 25mhz by 4 and have a 100mhz
> clock, that would be good...
>
> 4) given I have input pins on my fpga, could I make up a daughter
> card, that has a 100mhz oscillator on it, send that signal in on one
> of the pins and use that as the clock and ignore the 25mhz clock?
>
> Tia,
>
> Jonathan

If you're using a Xilinx FPGA, you can use a DCM block to multiply the
25MHz up
to 100 MHz.  The 100MHz can easily be divided down to 20MHz.

John Providenza

On Apr 2, 7:05 pm, jprovide...@yahoo.com wrote:
> On Apr 2, 3:46 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
>
>
> > Ok,
>
> > so I have a system that has a 25mhz clock built on it, and I'd like to
> > have either a 20mhz clock or a 100mhz clock,
>
> > Now I'm thinking of options,
>
> > 1) make a 20mhz clock out of the 25mhz.
> > - the obvious idea is to count up to 5 and force a state change on one
> > of the counts, but this will give me a 80/20 duty cycle. If i'm only
> > clocking on the rising edge, is this a problem?
>
> > 2) how would I make a 20mhz clock out of the 25mhz with a closer to
> > 50/50 duty cycle?
>
> > 3) I keep hearing about clock mulitpliers, how is that done in an
> > fpga?  I could on paper multiply the 25mhz by 4 and have a 100mhz
> > clock, that would be good...
>
> > 4) given I have input pins on my fpga, could I make up a daughter
> > card, that has a 100mhz oscillator on it, send that signal in on one
> > of the pins and use that as the clock and ignore the 25mhz clock?
>
> > Tia,
>
> > Jonathan
>
> If you're using a Xilinx FPGA, you can use a DCM block to multiply the
> 25MHz up
> to 100 MHz.  The 100MHz can easily be divided down to 20MHz.
>
> John Providenza

Ok, yeah, that is what I'm reading up on.

there is no good way to divide 25mhz to get 20mhz, that was
incorrect.
I'm still interested in an external oscillator coming in on a pin
though.

I'm seeing some write-ups on dll (delay latch logic?) but I'm
unfamiliar with
DCM (and dll) for that matter.  Here is what xilinx has as code:


-----------------------------------------------------------------------------------
-- XAPP174
--
-- DLL 2X and 4X Example
--
library ieee;
use ieee.std_logic_1164.all;

entity dll_standard is
    port (CLKIN : in  std_logic;
          RESET : in  std_logic;
          CLK2X : out std_logic;
          CLK4X : out std_logic;
          LOCKED: out std_logic);
end dll_standard;

architecture structural of dll_standard is


component IBUFG
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;

component IBUF
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;

component CLKDLL
    port ( CLKIN   : in  std_ulogic := '0';
           CLKFB   : in  std_ulogic := '0';
           RST     : in  std_ulogic := '0';
           CLK0    : out std_ulogic := '0';
           CLK90   : out std_ulogic := '0';
           CLK180  : out std_ulogic := '0';
           CLK270  : out std_ulogic := '0';
           CLK2X   : out std_ulogic := '0';
           CLKDV   : out std_ulogic := '0';
           LOCKED  : out std_ulogic := '0');
end component;
component BUFG
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;
component OBUF
   port(
      O                              :	out   STD_ULOGIC;
      I                              :	in    STD_ULOGIC);
end component;

component SRL16
  port (D   : in STD_ULOGIC;
        CLK : in STD_ULOGIC;
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        Q   : out STD_ULOGIC);
end component;


signal CLKIN_w, RESET_w, CLK2X_dll, CLK2X_g, CLK4X_dll, CLK4X_g :
std_logic;
signal LOCKED2X, LOCKED2X_delay, RESET4X, LOCKED4X_dll : std_logic;
signal logic1 : std_logic;

begin

logic1 <= '1';

clkpad : IBUFG  port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF   port map (I=>RESET, O=>RESET_w);

dll2x  : CLKDLL port map (CLKIN=>CLKIN_w,   CLKFB=>CLK2X_g,
RST=>RESET_w,
                          CLK0=>open,   CLK90=>open, CLK180=>open,
CLK270=>open,
                          CLK2X=>CLK2X_dll, CLKDV=>open,
LOCKED=>LOCKED2X);

clk2xg : BUFG   port map (I=>CLK2X_dll,   O=>CLK2X_g);

rstsrl : SRL16  port map (D=>LOCKED2X, CLK=>CLK2X_g,
Q=>LOCKED2X_delay,
                          A3=>logic1, A2=>logic1, A1=>logic1,
A0=>logic1);

RESET4X <= not LOCKED2X_delay;

dll4x  : CLKDLL port map (CLKIN=>CLK2X_g,  CLKFB=>CLK4X_g,
RST=>RESET4X,
                          CLK0=>open,   CLK90=>open, CLK180=>open,
CLK270=>open,
                          CLK2X=>CLK4X_dll, CLKDV=>open,
LOCKED=>LOCKED4X_dll);


clk4xg : BUFG   port map (I=>CLK4X_dll,  O=>CLK4X_g);
lckpad : OBUF   port map (I=>LOCKED4X_dll, O=>LOCKED);

CLK2X <= CLK2X_g;
CLK4X <= CLK4X_g;

end structural;
-----------------------------------------------------------------------------------------------------


so what, I just make up an instance on this routine, send in my 25mhz
clock, and out comes
a 100mhz clock?   And then my program references this 100mhz clock
instead?

That's all there is to it?

jleslie48 wrote:

> so I have a system that has a 25mhz clock built on it, and I'd like to 
> have either a 20mhz clock or a 100mhz clock,
> 
> Now I'm thinking of options,
> 
> 1) make a 20mhz clock out of the 25mhz. - the obvious idea is to count
> up to 5 and force a state change on one of the counts, but this will
> give me a 80/20 duty cycle. If i'm only clocking on the rising edge, is
> this a problem?

Depends entirely on your application. And BTW, I'd suggest if you use this
method, you generate a 20MHz clock _enable_, rather than a clock...

> 2) how would I make a 20mhz clock out of the 25mhz with a closer to 
> 50/50 duty cycle?

DCM

> 3) I keep hearing about clock mulitpliers, how is that done in an fpga?
> I could on paper multiply the 25mhz by 4 and have a 100mhz clock, that
> would be good...

The Xilinx DCM will _surely_ be able to produce a 20MHz clock from the
25MHz clock (I'm an Altera guy). That's exactly what they're for! You
shouldn't need to be worrying about feeding in different clocks...

> 4) given I have input pins on my fpga, could I make up a daughter card,
> that has a 100mhz oscillator on it, send that signal in on one of the
> pins and use that as the clock and ignore the 25mhz clock?

You can only use certain pins for clocks, you can't just feed it in on any
old pin and use it as a (global) clock.

Use a DCM!!! It will do everything you need.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

On Thu, 2 Apr 2009 16:23:20 -0700 (PDT)
jleslie48 <jon@jonathanleslie.com> wrote:

> On Apr 2, 7:05 pm, jprovide...@yahoo.com wrote:
> > On Apr 2, 3:46 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> >
> >
> >
> > > Ok,
> >
> > > so I have a system that has a 25mhz clock built on it, and I'd
> > > like to have either a 20mhz clock or a 100mhz clock,
> >
> > > Now I'm thinking of options,
> >
> > > 1) make a 20mhz clock out of the 25mhz.
> > > - the obvious idea is to count up to 5 and force a state change
> > > on one of the counts, but this will give me a 80/20 duty cycle.
> > > If i'm only clocking on the rising edge, is this a problem?
> >
> > > 2) how would I make a 20mhz clock out of the 25mhz with a closer
> > > to 50/50 duty cycle?
> >
> > > 3) I keep hearing about clock mulitpliers, how is that done in an
> > > fpga?  I could on paper multiply the 25mhz by 4 and have a 100mhz
> > > clock, that would be good...
> >
> > > 4) given I have input pins on my fpga, could I make up a daughter
> > > card, that has a 100mhz oscillator on it, send that signal in on
> > > one of the pins and use that as the clock and ignore the 25mhz
> > > clock?
> >
> > > Tia,
> >
> > > Jonathan
> >
> > If you're using a Xilinx FPGA, you can use a DCM block to multiply
> > the 25MHz up
> > to 100 MHz.  The 100MHz can easily be divided down to 20MHz.
> >
> > John Providenza
> 
> Ok, yeah, that is what I'm reading up on.
> 
> there is no good way to divide 25mhz to get 20mhz, that was
> incorrect.
> I'm still interested in an external oscillator coming in on a pin
> though.
> 
> I'm seeing some write-ups on dll (delay latch logic?) but I'm
> unfamiliar with
> DCM (and dll) for that matter.  Here is what xilinx has as code:
> 
> [snip]
> so what, I just make up an instance on this routine, send in my 25mhz
> clock, and out comes
> a 100mhz clock?   And then my program references this 100mhz clock
> instead?
> 
> That's all there is to it?
> 

Pretty much, although some of that instance didn't look quite right.
Most people use CoreGen to put together a nice clean wrapper over top
of the DCM instance (it might be the only thing CoreGen's good for).

Check out the chapter on the DCMs in UG331, the Spartan3 User's Guide.
It's got a lot of information that will be of use to you.


-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Apr 2, 9:20 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Thu, 2 Apr 2009 16:23:20 -0700 (PDT)
>
>
>
> jleslie48 <j...@jonathanleslie.com> wrote:
> > On Apr 2, 7:05 pm, jprovide...@yahoo.com wrote:
> > > On Apr 2, 3:46 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> > > > Ok,
>
> > > > so I have a system that has a 25mhz clock built on it, and I'd
> > > > like to have either a 20mhz clock or a 100mhz clock,
>
> > > > Now I'm thinking of options,
>
> > > > 1) make a 20mhz clock out of the 25mhz.
> > > > - the obvious idea is to count up to 5 and force a state change
> > > > on one of the counts, but this will give me a 80/20 duty cycle.
> > > > If i'm only clocking on the rising edge, is this a problem?
>
> > > > 2) how would I make a 20mhz clock out of the 25mhz with a closer
> > > > to 50/50 duty cycle?
>
> > > > 3) I keep hearing about clock mulitpliers, how is that done in an
> > > > fpga?  I could on paper multiply the 25mhz by 4 and have a 100mhz
> > > > clock, that would be good...
>
> > > > 4) given I have input pins on my fpga, could I make up a daughter
> > > > card, that has a 100mhz oscillator on it, send that signal in on
> > > > one of the pins and use that as the clock and ignore the 25mhz
> > > > clock?
>
> > > > Tia,
>
> > > > Jonathan
>
> > > If you're using a Xilinx FPGA, you can use a DCM block to multiply
> > > the 25MHz up
> > > to 100 MHz.  The 100MHz can easily be divided down to 20MHz.
>
> > > John Providenza
>
> > Ok, yeah, that is what I'm reading up on.
>
> > there is no good way to divide 25mhz to get 20mhz, that was
> > incorrect.
> > I'm still interested in an external oscillator coming in on a pin
> > though.
>
> > I'm seeing some write-ups on dll (delay latch logic?) but I'm
> > unfamiliar with
> > DCM (and dll) for that matter.  Here is what xilinx has as code:
>
> > [snip]
> > so what, I just make up an instance on this routine, send in my 25mhz
> > clock, and out comes
> > a 100mhz clock?   And then my program references this 100mhz clock
> > instead?
>
> > That's all there is to it?
>
> Pretty much, although some of that instance didn't look quite right.
> Most people use CoreGen to put together a nice clean wrapper over top
> of the DCM instance (it might be the only thing CoreGen's good for).
>
> Check out the chapter on the DCMs in UG331, the Spartan3 User's Guide.
> It's got a lot of information that will be of use to you.
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

hey thanks guys.
ok so I have some reading to do.  ug331, and that will explain what a
DCM is.  It seems all agree that is the way to the solution.  I forgot
to mention I am on a Spartan3 chip anyway, so much the better for the
reading.

Sincerely,

Jonathan Leslie

On Apr 2, 8:53 pm, Mark McDougall <ma...@vl.com.au> wrote:
> jleslie48 wrote:
> > so I have a system that has a 25mhz clock built on it, and I'd like to
> > have either a 20mhz clock or a 100mhz clock,
>
> > Now I'm thinking of options,
>
> > 1) make a 20mhz clock out of the 25mhz. - the obvious idea is to count
> > up to 5 and force a state change on one of the counts, but this will
> > give me a 80/20 duty cycle. If i'm only clocking on the rising edge, is
> > this a problem?
>
> Depends entirely on your application. And BTW, I'd suggest if you use this
> method, you generate a 20MHz clock _enable_, rather than a clock...

That is a very good point.  If you need multiple clock circuits
internally, you might be better off using a high rate clock with a
common factor and internally using clock enables.  If you need to move
data around using these clocks they can be independent until you need
to move that data between one clock domain and another.


> > 2) how would I make a 20mhz clock out of the 25mhz with a closer to
> > 50/50 duty cycle?
>
> DCM

The method used for generating one frequency from another that doesn't
just involve dividing down a rate typically is a PLL.  I know that
most FPGA types include a PLL.  Depending on the chip family, Xilinx
uses a DLL which is very similar.

The way a PLL works is to run a VCO (voltage controlled oscillator) as
part of a feedback loop.  The output rate of the VCO is divided down
to a reference frequency and compared to the input divided down to the
same reference frequency.  The phase comparitor outputs a voltage to
control the VCO.  When the frequencies are not matched, the phase
comparator sees a difference in phase and adjusts the output voltage.
So the output frequency changes until the two reference frequencies
match.  A low pass filter between the phase comparator and the VCO
helps to smooth the adjustments in frequency.

In this case, the 25 MHz can be used directly as the input reference
frequency.  The output is divided by four so that it run at 100 MHz
when the divided clock matches the 25 MHz reference.


> > 3) I keep hearing about clock mulitpliers, how is that done in an fpga?
> > I could on paper multiply the 25mhz by 4 and have a 100mhz clock, that
> > would be good...
>
> The Xilinx DCM will _surely_ be able to produce a 20MHz clock from the
> 25MHz clock (I'm an Altera guy). That's exactly what they're for! You
> shouldn't need to be worrying about feeding in different clocks...
>
> > 4) given I have input pins on my fpga, could I make up a daughter card,
> > that has a 100mhz oscillator on it, send that signal in on one of the
> > pins and use that as the clock and ignore the 25mhz clock?
>
> You can only use certain pins for clocks, you can't just feed it in on any
> old pin and use it as a (global) clock.

Are you sure about that?  I haven't looked at this detail on a Xilinx
part in a while, but the Lattice parts allow a clock source to be from
the general routing.  Because of the long delay in the routing, this
won't be usable to clock input data that is relative to that clock,
but it can be used internally.

This is one of those situations where a little knowledge is a
dangerous thing.  There is so much more to clocking an FPGA than just
getting a clock rate.  It would be best if we understood the bigger
problem.  That could easily save going down a more complex and
difficult path when it is not needed at all.

Rick

On Apr 2, 10:06=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > You can only use certain pins for clocks, you can't just feed it in on =
any
> > old pin and use it as a (global) clock.
>
> Are you sure about that? =A0I haven't looked at this detail on a Xilinx
> part in a while, but the Lattice parts allow a clock source to be from
> the general routing. =A0Because of the long delay in the routing, this
> won't be usable to clock input data that is relative to that clock,
> but it can be used internally.
>
> This is one of those situations where a little knowledge is a
> dangerous thing. =A0There is so much more to clocking an FPGA than just
> getting a clock rate. =A0It would be best if we understood the bigger
> problem. =A0That could easily save going down a more complex and
> difficult path when it is not needed at all.
>
> Rick

You need to set an environment variable to allow connecting
just any input pin to a DCM.  If the frequency is all you
care about, i.e. there is no external signal synchronous
to the 25 MHz oscillator, then any pin will do, but it
is "not recommended" by Xilinx.  If you haven't already
defined the pinout, best to use a global clock input for
this.

Regards,
Gabor

Jonathan

The DCM comes in almost two parts and the best part for this is the
clock sythesiser part. Basically it's the CLKFX output you are looking
to use. I'd suggest a multiply number of 4 and a divide number of 5 to
achieve 20MHz.

A good source of information is the user guide ug331.pdf. Google that
and you should find it. You can also look at the libraries guide,
usually found under help in ISE, for information on primatives. You
can also find some VHDL and Verilog templates under the light bulb
icon in ISE than may help.

There is also the "Architecture Wizard" which is under ISE-Accessories
can do some generation of templetes for some modes of the DCM although
I don't think frequency synthesis is one covered.

Most DCM modes will give near 50:50 clock except when locking and you
get some real oddballs then.

John Adair
Enterpoint Ltd.

On 2 Apr, 23:46, jleslie48 <j...@jonathanleslie.com> wrote:
> Ok,
>
> so I have a system that has a 25mhz clock built on it, and I'd like to
> have either a 20mhz clock or a 100mhz clock,
>
> Now I'm thinking of options,
>
> 1) make a 20mhz clock out of the 25mhz.
> - the obvious idea is to count up to 5 and force a state change on one
> of the counts, but this will give me a 80/20 duty cycle. If i'm only
> clocking on the rising edge, is this a problem?
>
> 2) how would I make a 20mhz clock out of the 25mhz with a closer to
> 50/50 duty cycle?
>
> 3) I keep hearing about clock mulitpliers, how is that done in an
> fpga? =A0I could on paper multiply the 25mhz by 4 and have a 100mhz
> clock, that would be good...
>
> 4) given I have input pins on my fpga, could I make up a daughter
> card, that has a 100mhz oscillator on it, send that signal in on one
> of the pins and use that as the clock and ignore the 25mhz clock?
>
> Tia,
>
> Jonathan

Dont forget to use proper feedback (internal or external) while using
DCM (the architecture wizard will cover all that using a GUI). If your
design is timing critical and a full blown product, you might want to
include locked signal in your clock enables for fail safe operation.

Hope this helps

Mak

On Apr 3, 3:46=A0am, jleslie48 <j...@jonathanleslie.com> wrote:
> Ok,
>
> so I have a system that has a 25mhz clock built on it, and I'd like to
> have either a 20mhz clock or a 100mhz clock,
>
> Now I'm thinking of options,
>
> 1) make a 20mhz clock out of the 25mhz.
> - the obvious idea is to count up to 5 and force a state change on one
> of the counts, but this will give me a 80/20 duty cycle. If i'm only
> clocking on the rising edge, is this a problem?
>
> 2) how would I make a 20mhz clock out of the 25mhz with a closer to
> 50/50 duty cycle?
>
> 3) I keep hearing about clock mulitpliers, how is that done in an
> fpga? =A0I could on paper multiply the 25mhz by 4 and have a 100mhz
> clock, that would be good...
>
> 4) given I have input pins on my fpga, could I make up a daughter
> card, that has a 100mhz oscillator on it, send that signal in on one
> of the pins and use that as the clock and ignore the 25mhz clock?
>
> Tia,
>
> Jonathan