Chipscope problem

Hi,

I wanted to use chipscope to verify my design (on Xilinx Virtex4 using
ISE 10.1 and XST), but something strange happens which I don't have
any idea about that. I generated the ICON and ILA cores by core
generator and then instantiated them and connected some signals to the
ILA core. Everything seemed fine until I wanted to download the
bitsream. The bitstream cannot be downloaded. When I attempt to
download it, it waits for a few seconds and then an error message
appears ( I guess the Done signal is not asserted). First, is it
possible for the tools to generate a faulty bitstream? Second, how
come the chipscope cores affect the design in this way? (If I simply
remove the debug cores, things will work perfect again)

Later, I looked at the DRC file generated by bitgen. There are are a
number of warnings in the DRC file. The warnings are mainly about
unconnected signals. The time I'm not using chipscope there are 48
warnings and when I'm using it there are 191. The thing surprised me
was that these additional warnings MUST always exist regardless of
using debug cores. Because they refer to some unconnected output pins
of BRAMs which is always the same in my design. In fact, I'm using
dual port BRAMs (18-bit wide) for which output of port a is fully
connected while only 9 LSB bits of output b is used.

Sounds like you've messed up the JTAG connection... Are you using ISE GUI? 
If you are using GUI there is no need to generate and connect ICON and ILA 
cores manually. Instead add a Chipscope definition and connection file as a 
new source using the new source wizard. Simply right click on the top of 
your project tree and choose new source, then choose the Chipscope. It will 
guide you through the whole thing.

/Mikhail



"Ehsan" <ehsan.hosseini@gmail.com> wrote in message 
news:c16aab71-0e15-4828-9583-4be7c037dbb3@v1g2000prd.googlegroups.com...
> Hi,
>
> I wanted to use chipscope to verify my design (on Xilinx Virtex4 using
> ISE 10.1 and XST), but something strange happens which I don't have
> any idea about that. I generated the ICON and ILA cores by core
> generator and then instantiated them and connected some signals to the
> ILA core. Everything seemed fine until I wanted to download the
> bitsream. The bitstream cannot be downloaded. When I attempt to
> download it, it waits for a few seconds and then an error message
> appears ( I guess the Done signal is not asserted). First, is it
> possible for the tools to generate a faulty bitstream? Second, how
> come the chipscope cores affect the design in this way? (If I simply
> remove the debug cores, things will work perfect again)
>
> Later, I looked at the DRC file generated by bitgen. There are are a
> number of warnings in the DRC file. The warnings are mainly about
> unconnected signals. The time I'm not using chipscope there are 48
> warnings and when I'm using it there are 191. The thing surprised me
> was that these additional warnings MUST always exist regardless of
> using debug cores. Because they refer to some unconnected output pins
> of BRAMs which is always the same in my design. In fact, I'm using
> dual port BRAMs (18-bit wide) for which output of port a is fully
> connected while only 9 LSB bits of output b is used. 

On Apr 5, 6:04=A0am, "MM" <mb...@yahoo.com> wrote:
> Sounds like you've messed up the JTAG connection... Are you using ISE GUI=
?
> If you are using GUI there is no need to generate and connect ICON and IL=
A
> cores manually. Instead add a Chipscope definition and connection file as=
 a
> new source using the new source wizard. Simply right click on the top of
> your project tree and choose new source, then choose the Chipscope. It wi=
ll
> guide you through the whole thing.
>
> /Mikhail
>
> "Ehsan" <ehsan.hosse...@gmail.com> wrote in message
>
> news:c16aab71-0e15-4828-9583-4be7c037dbb3@v1g2000prd.googlegroups.com...
>
>
>
> > Hi,
>
> > I wanted to use chipscope to verify my design (on Xilinx Virtex4 using
> > ISE 10.1 and XST), but something strange happens which I don't have
> > any idea about that. I generated the ICON and ILA cores by core
> > generator and then instantiated them and connected some signals to the
> > ILA core. Everything seemed fine until I wanted to download the
> > bitsream. The bitstream cannot be downloaded. When I attempt to
> > download it, it waits for a few seconds and then an error message
> > appears ( I guess the Done signal is not asserted). First, is it
> > possible for the tools to generate a faulty bitstream? Second, how
> > come the chipscope cores affect the design in this way? (If I simply
> > remove the debug cores, things will work perfect again)
>
> > Later, I looked at the DRC file generated by bitgen. There are are a
> > number of warnings in the DRC file. The warnings are mainly about
> > unconnected signals. The time I'm not using chipscope there are 48
> > warnings and when I'm using it there are 191. The thing surprised me
> > was that these additional warnings MUST always exist regardless of
> > using debug cores. Because they refer to some unconnected output pins
> > of BRAMs which is always the same in my design. In fact, I'm using
> > dual port BRAMs (18-bit wide) for which output of port a is fully
> > connected while only 9 LSB bits of output b is used.- Hide quoted text =
-
>
> - Show quoted text -

Yes! I'm using the GUI and did the same you've just written. I've used
Chipscope quite a few times and never had experienced this kind of
problem.

>Yes! I'm using the GUI and did the same you've just written. I've used
>Chipscope quite a few times and never had experienced this kind of
>problem.

So, is it working now or not? If not try cleaning project files and 
rebuilding everything from scratch.


/Mikhail 

On Apr 6, 12:23=A0am, "MM" <mb...@yahoo.com> wrote:
> >Yes! I'm using the GUI and did the same you've just written. I've used
> >Chipscope quite a few times and never had experienced this kind of
> >problem.
>
> So, is it working now or not? If not try cleaning project files and
> rebuilding everything from scratch.
>
> /Mikhail

Nope, It's not working at all. And I cleaned everything a couple of
times, but notihng changed.

You said the following in the original post:
>I generated the ICON and ILA cores by core
>generator and then instantiated them and connected some signals to the
>ILA core.

From this it doesn't sound as you had used the wizard? Had you or had you 
not?

Also, does your Chipscope version match the ISE version?

/Mikhail 

On Apr 6, 11:56=A0am, "MM" <mb...@yahoo.com> wrote:
> You said the following in the original post:
>
> >I generated the ICON and ILA cores by core
> >generator and then instantiated them and connected some signals to the
> >ILA core.
>
> From this it doesn't sound as you had used the wizard? Had you or had you
> not?
>
> Also, does your Chipscope version match the ISE version?
>
> /Mikhail

I guess you are referring to ISE versions lower than 10.1. In 10.1,
you need to generate Chipscope cores like any other ip cores via the
coregen which you can run it either within the Project Navigator or
standalone. There is no more Chipscope GUI for generating debug cores.
The Chipscope has the same version. It was actually installed when I
installed the ISE. I don't remember if we had to pay for the license
or it just came for free.

Ehsan

I think he is using CoreGenerator. Have you tried using Core Inserter?
Core Inserter is the app launched from the Chipscope folder and is
much easier to use (my opinion). You can drag and drop the signals you
wish to probe from their GUI instead of manually wiring up to ILA
ports in your RTL.

> I guess you are referring to ISE versions lower than 10.1. In 10.1,
> you need to generate Chipscope cores like any other ip cores via the
> coregen which you can run it either within the Project Navigator or
> standalone. There is no more Chipscope GUI for generating debug cores.

As another poster rightly pointed out, essentially you need to run the 
chipscope core inserter. That's what gets called by the new file wizard in 
ISE8.2 anyway. I can't verify if it is indeed broken in 10.1 at the moment, 
but perhaps you are right. If that's the case just run the Chipscope 
inserter standalone.


/Mikhail

I'm currently using an ILA and inserting it using 10.1 software, I'm
not having any issues.