Modulo-10 counter

Hello, my question is I'm making a modulo-10 counter using a CB4CLE counter 
(http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0080_48.html) and 
some logic gates. I am making a modulo-10 counter because I need a 1 Hz 
clock for my design (the clock input to the counter is a 10 Hz signal). The 
problem is that, when I implement my design to a FPGA, my tool warns me that 
there may be a problem due to clock skew, because the clock is being 
generated after a combinational network (two levels of AND gates to detect 
when the counter reaches 10).

My question is simple, is there any other method to build a modulo-10 
counter from CB4CLE modules or I can simply ignore the warning?

Thank, 

>
> My question is simple, is there any other method to build a modulo-10 
> counter from CB4CLE modules or I can simply ignore the warning?
>

Very easy...write the code for a modulo 10 counter in VHDL or Verilog and 
stop trying to use vendor specific widgets like CB4CLE that don't do what 
you want them to do anyway.

...snippet of VHDL example...

signal Count: natural range 0 to 10;
...
Modulo_10_Counter : process(Clock)
begin
    if rising_edge(Clock) then
      if (Reset = '1') then
        Count <= 0;
     elsif(Clock_Enable = '1') then
       if (Count = 9) then
         Count <= 0;
      else
         Count <= Count + 1;
      end if;
  end if;
end process Modulo_10_Counter;

Kevin Jennings 

> my tool warns me that
> there may be a problem due to clock skew, because the clock is being 
> generated after a combinational network (two levels of AND gates to detect 
> when the counter reaches 10).

Forgot to address this in the earlier post.  This warning indicates that 
you're not using a synchronous design process (because you're making gated 
clocks) which is almost without exception a very big mistake in FPGAs.  The 
warning should not be ignored, because it means that your design is likely 
to not work reliably (like, it works when it is first turned on and then 
stops working later...or just the opposite).  In any case, the VHDL code I 
posted in previously addresses this point as well...but assumes that the 
signal 'Clock' is not generated by any logic of any sort (i.e. it comes from 
an input pin that comes from a crystal or oscillator or is the output of a 
PLL).

KJ 

Thanks, but I have to do it with schematics......

"KJ" <kkjennings@sbcglobal.net> wrote in message 
news:B3UBl.3614$im1.441@nlpi061.nbdc.sbc.com...
> >
>> My question is simple, is there any other method to build a modulo-10 
>> counter from CB4CLE modules or I can simply ignore the warning?
>>
>
> Very easy...write the code for a modulo 10 counter in VHDL or Verilog and 
> stop trying to use vendor specific widgets like CB4CLE that don't do what 
> you want them to do anyway.
>
> ...snippet of VHDL example...
>
> signal Count: natural range 0 to 10;
> ...
> Modulo_10_Counter : process(Clock)
> begin
>    if rising_edge(Clock) then
>      if (Reset = '1') then
>        Count <= 0;
>     elsif(Clock_Enable = '1') then
>       if (Count = 9) then
>         Count <= 0;
>      else
>         Count <= Count + 1;
>      end if;
>  end if;
> end process Modulo_10_Counter;
>
> Kevin Jennings
> 

On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote:

>Thanks, but I have to do it with schematics.....

Oh dear.  Why?

Basic Metalwork course, Lab 1:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
You are given a piece of steel approximately
5cm x 5cm x 5cm.  Your task is to construct
a steel cylinder, of diameter 3cm and length
4cm, without using a lathe.  Marks will be 
deducted for any evidence that you borrowed
your friend's CNC milling machine.  Extra
credit is available for completing the task
using tools made only from elk antlers.

-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley wrote:

> 
> Basic Metalwork course, Lab 1:
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> You are given a piece of steel approximately
> 5cm x 5cm x 5cm.  Your task is to construct
> a steel cylinder, of diameter 3cm and length
> 4cm, without using a lathe.  Marks will be 
> deducted for any evidence that you borrowed
> your friend's CNC milling machine.  Extra
> credit is available for completing the task
> using tools made only from elk antlers.
> 
:-)

So true.

But just imagine, you're lost in a snow storm and a cylinder of your car
is broken.
Then you won't have any CNC machine and you'd be sooo glad to not have
cheated with a CNC machine during your metalwork course.

:-) :-)

On Apr 5, 2:16=A0am, "Xin Xiao" <n...@no.com> wrote:
> Hello, my question is I'm making a modulo-10 counter using a CB4CLE count=
er
> (http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0080_48.html) a=
nd
> some logic gates. I am making a modulo-10 counter because I need a 1 Hz
> clock for my design (the clock input to the counter is a 10 Hz signal). T=
he
> problem is that, when I implement my design to a FPGA, my tool warns me t=
hat
> there may be a problem due to clock skew, because the clock is being
> generated after a combinational network (two levels of AND gates to detec=
t
> when the counter reaches 10).
>
> My question is simple, is there any other method to build a modulo-10
> counter from CB4CLE modules or I can simply ignore the warning?
>
> Thank,

Hi Xin,
as pointed out by KJ it is not a wise idea not to use the global clock
nets for clock signals.
However it's very tricky to do so with signals created by your own
logic.
But there is a well working solution to your problem.

Build your modulo 10 counter so, that it generates a some kind of
ripple signal that is active for only one 10Hz period.
Use this signal as a Clock Enable for all the FFs that shall run with
1Hz. The Clock for these FFs is your 10Hz Master Clock.

There are papers available, e.g. from xilinx, that discuss this method
in detail.
____
Truly, schematic input is not the method of choice for designing FPGA
logic, but it's not your fault that you are forced to use it.
If you are a student, schematics are helpful to understand digital
logic. But if that task is mixed up with understanding how FPGAs work
it is like learning to walk during an olympic sprinting competition.

_____
One more comment :
Ok, you get this warning about possible dangers arising from clock
skew.
This is definitly true, and would affect your design if you would play
in the X- MHz league.
But for your 10Hz design you probably could have 64bit combinatorical
multipliers in your datapath without being bothered by clock skew
problems.
Data would be stable way loooong before the next clock edge.
(Actually, some logic between your FFs would be very useful in this
case.)
There's a very good article in the english wikipedia about Clock Skew.
Read it for further understanding.

Have a nice synthesis
   Eilert

On Sun, 5 Apr 2009 23:42:12 -0700 (PDT), goouse@twinmail.de wrote:

>Ok, you get this warning about possible dangers arising from clock
>skew.
>This is definitly true, and would affect your design if you would play
>in the X- MHz league.
>But for your 10Hz design you probably could have 64bit combinatorical
>multipliers in your datapath without being bothered by clock skew
>problems.

OUCH - dangerous myth... as Eilert knows well, I hope.

Clock skew is likely to lead to hold time violations,
which break the design's functionality on EACH INDIVIDUAL
clock edge.  Hold problems are not related to the time
between clocks, and cannot be fixed by running the clock
more slowly.

>(Actually, some logic between your FFs would be 
>very useful in this case.)

Yes; hold-time fixup.  Some FPGA tools already do this for you
to some extent.

For a small, slow design, the message is clear: 
USE CLOCK ENABLES.  Get your divide-by-10 circuit to
generate a synchronous pulse that is true for 1 cycle
of the 10Hz clock, and false for 9 cycles.  Use that
pulse as the clock enable for any logic that you want
to run at 1Hz.  Use the single, common 10Hz clock 
as the clock input for every flip-flop in the design.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:4g4it4d9ah49jmotmo9btar8lmd8qoa3cm@4ax.com...
> On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote:
>
>>Thanks, but I have to do it with schematics.....
>
> Oh dear.  Why?
>
> Basic Metalwork course, Lab 1:
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> You are given a piece of steel approximately
> 5cm x 5cm x 5cm.  Your task is to construct
> a steel cylinder, of diameter 3cm and length
> 4cm, without using a lathe.  Marks will be
> deducted for any evidence that you borrowed
> your friend's CNC milling machine.  Extra
> credit is available for completing the task
> using tools made only from elk antlers.
>
> -- 
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.bromley@MYCOMPANY.com
> http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

????
If he was using Altera Quartus schematic then it would take less than 10 
seconds using the LPM_COUNTER wizard - about 100 times faster than using 
crap VHDL. 

On Mon, 6 Apr 2009 17:03:28 +0100, "Dave Wilson" wrote:

>????
>If he was using Altera Quartus schematic then it would take less than 10 
>seconds using the LPM_COUNTER wizard - about 100 times faster than using 
>crap VHDL. 

That's the purest humbug.  You can't even START the wizard in 
ten seconds.  Then you have to wade through a gazillion 
dialogs.  Then you have to drop the stupid thing on a sheet
and wire it up.  Any wizard, no matter how clever, must 
guide the user through all the choices that the same user
could have made with a few keystrokes of text.

Give me text any day.  Verilog, VHDL, even PALASM if you
really must torture me.  But spare me the schematics.
They have their uses when doodling on restaurant napkins,
and maybe for some kinds of top-level block-stitching,
but not for anything much else.

Schematics live in my head, as a thinking tool, and 
occasionally leak out on to paper as a tool for communicating
with myself or with fellow humans.  They are a lousy design 
entry tool.  And that's even before you start to deal with
the general crumminess of most schematic capture packages,
where tools for ripping and re-numbering buses are
palaeolithic, and re-use means working out how to bring
up impenetrable property sheets instead of simply patching
and commenting the generics on VHDL components.

I guess we'll have to agree to differ, but I gave up
serious use of schematics a decade ago and I don't miss
them even a tiny little bit.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.