Hello all,
I'm still working with DSPBuilder. Here's a VHDL problem
that I can fix but don't understand. DSPBuilder.vhd has a line
obj:lpm_add_sub <snip> port map (cin => '1');
Quartus is happy with this, and in fact I use constant port values
in my own VHDL all the time. But Model Technology (Altera Edition 5.7e)
complains:
# ** Error: Actual for formal cin is not a signal.
# ** Error: Value associated with cin does not have a static name.
So first I tried
constant one : std_logic := '1';
...
obj:lpm_add_sub <snip> port map (cin => one);
and got
# ** Error: Actual for formal cin is not a signal.
And finally
signal one : std_logic := '1';
...
obj:lpm_add_sub <snip> port map (cin => one);
which worked.
My questions are:
(1) Why is port map(cin=>'1') not considered OK ?
(2) Is it bad practice to do this ?
Thanks in advance for any pointers.
Btw, The component declaration for lpm_add_sub is
COMPONENT lpm_add_sub
GENERIC ( <snip> );
PORT ( <snip>
cin: IN STD_LOGIC := '0';
<snip>
);
END COMPONENT;
-rajeev-
VHDL: Use of literal '1' on an input port ?
Started by ●April 5, 2004
Reply by ●April 5, 20042004-04-05
Rajeev, Make sure to turn on the VHDL-93 switch. You can do this in the compile options menu item under compile in 5.7. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Rajeev wrote:> Hello all, > > I'm still working with DSPBuilder. Here's a VHDL problem > that I can fix but don't understand. DSPBuilder.vhd has a line > > obj:lpm_add_sub <snip> port map (cin => '1'); > > Quartus is happy with this, and in fact I use constant port values > in my own VHDL all the time. But Model Technology (Altera Edition 5.7e) > complains: > > # ** Error: Actual for formal cin is not a signal. > # ** Error: Value associated with cin does not have a static name. > > So first I tried > > constant one : std_logic := '1'; > ... > obj:lpm_add_sub <snip> port map (cin => one); > > and got > # ** Error: Actual for formal cin is not a signal. > > And finally > > signal one : std_logic := '1'; > ... > obj:lpm_add_sub <snip> port map (cin => one); > > which worked. > > My questions are: > > (1) Why is port map(cin=>'1') not considered OK ? > > (2) Is it bad practice to do this ? > > Thanks in advance for any pointers. > > Btw, The component declaration for lpm_add_sub is > > COMPONENT lpm_add_sub > GENERIC ( <snip> ); > PORT ( <snip> > cin: IN STD_LOGIC := '0'; > <snip> > ); > END COMPONENT; > > -rajeev-
Reply by ●April 6, 20042004-04-06
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<407172DA.4060907@SynthWorks.com>...> Rajeev, > Make sure to turn on the VHDL-93 switch. > > You can do this in the compile options menu item under > compile in 5.7. > > Cheers, > JimJim, Thanks much ! That did it. -rajeev- <...>
Reply by ●April 6, 20042004-04-06
On Mon, 05 Apr 2004 07:53:14 -0700, Jim Lewis <Jim@SynthWorks.com> wrote:>Rajeev, >Make sure to turn on the VHDL-93 switch. > >You can do this in the compile options menu item under >compile in 5.7.Why do you suppose Modelsim defaults to -93 off? Perhaps someone should report this as a bug. Allan.
Reply by ●April 7, 20042004-04-07
"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:vdp670hd4nld9gof12hc92dgt04pbtu6rv@4ax.com...> On Mon, 05 Apr 2004 07:53:14 -0700, Jim Lewis <Jim@SynthWorks.com> > wrote: > > >Rajeev, > >Make sure to turn on the VHDL-93 switch. > > > >You can do this in the compile options menu item under > >compile in 5.7. > > Why do you suppose Modelsim defaults to -93 off? > Perhaps someone should report this as a bug. > > Allan.In Modelsim 5.8 it defaults to VHDL 2002, so I guess your wish is granted :-) regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●April 7, 20042004-04-07
On Wed, 07 Apr 2004 12:22:43 +1000, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: [...]>Why do you suppose Modelsim defaults to -93 off?It doesn't any more - since about version 5.8, the default has been VHDL-2001.>Perhaps someone should report this as a bug.Hardly a "bug", when you can fix it by deleting just one comment character in the modelsim.ini file :-) But I have been known to call it a "bloody nuisance". -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●April 7, 20042004-04-07
All tool vendor decisions like this are market driven (as opposed to standards driven). It was VHDL -87 because for a long time because the majority of designs were done in ASICs and their users wanted the default to match what the market leader (at the time) of ASIC synthesis (Synopsys) could handle at the time. Now the majority of designs are done in FPGAs. The market leaders of the FPGA synthesis market seem to support current language features. So now by market request it changes to -2002, something much more useful. So the market driven picture is this. A vendor will not invest in new language features out of good will. They will invest only by market (user) request. So as VHDL (and Verilog/SV) evolve, if you see a feature you want, make sure to tell your EDA vendor you want it. This is particularly effective around the time you are renewing licenses - they seem to listen better to $$$. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Allan Herriman wrote:> On Mon, 05 Apr 2004 07:53:14 -0700, Jim Lewis <Jim@SynthWorks.com> > wrote: > > >>Rajeev, >>Make sure to turn on the VHDL-93 switch. >> >>You can do this in the compile options menu item under >>compile in 5.7. > > > Why do you suppose Modelsim defaults to -93 off? > Perhaps someone should report this as a bug. > > Allan.
