Strange order of BRAM data bus connections

I'm using two dual port BRAMs to connect a 16-bit CPU
to a 1-bit serial flash (AT45DB161D).

Flash side: 4096*1
CPU   side: 256*16 (512 bytes)

BRAM X is used to transmit data from CPU to FLASH, and
BRAM Y from FLASH to CPU.

I've connected the CPU data bus like this:

BRAM X
DBUS(8) ... DBUS(15), DBUS(0) .. DBUS(7)

BRAM Y
8 ... 15, 0 .. 7 (ie. the same)


Both reading and writing works fine.


However, for security reasons,
I wish to scramble the bus:


BRAM X
12, 1, 6, 9, 15, 4, 14, 7, 2, 5, 8, 11, 3, 10, 0, 13.

(all 16 DBUS bits, just not in order)


I presumed the BRAM Y should have the same DBUS
order, but then reading gets invalid data.
After some trial and error, I've found the required
order on the BRAM Y:

11, 9, 0, 15, 4, 2, 12, 5, 8, 13, 6, 10, 3, 7, 14, 1.


Can anyone explain why is the order of DBUS
on BRAM X & Y the same in the first case
and not in the second one?

All buses are std_logic_vector(15 downto 0)

On Apr 10, 8:17=A0pm, aleksa <aleks...@gmail.com> wrote:
> I'm using two dual port BRAMs to connect a 16-bit CPU
> to a 1-bit serial flash (AT45DB161D).
>
> Flash side: 4096*1
> CPU =A0 side: 256*16 (512 bytes)
>
> BRAM X is used to transmit data from CPU to FLASH, and
> BRAM Y from FLASH to CPU.
>
> I've connected the CPU data bus like this:
>
> BRAM X
> DBUS(8) ... DBUS(15), DBUS(0) .. DBUS(7)
>
> BRAM Y
> 8 ... 15, 0 .. 7 (ie. the same)
>
> Both reading and writing works fine.
>
> However, for security reasons,
> I wish to scramble the bus:
>
> BRAM X
> 12, 1, 6, 9, 15, 4, 14, 7, 2, 5, 8, 11, 3, 10, 0, 13.
>
> (all 16 DBUS bits, just not in order)
>
> I presumed the BRAM Y should have the same DBUS
> order, but then reading gets invalid data.
> After some trial and error, I've found the required
> order on the BRAM Y:
>
> 11, 9, 0, 15, 4, 2, 12, 5, 8, 13, 6, 10, 3, 7, 14, 1.
>
> Can anyone explain why is the order of DBUS
> on BRAM X & Y the same in the first case
> and not in the second one?
>
> All buses are std_logic_vector(15 downto 0)

security 101

data bit re-order : security =3D 0
xor with const: security =3D 0
xor with fixed lenght constant string: security =3D 0
xor data with address bits: security =3D 0
...


most of the systems are cloned because the designers just dont include
any security

Antti

On Apr 10, 7:17=A0pm, aleksa <aleks...@gmail.com> wrote:
> I'm using two dual port BRAMs to connect a 16-bit CPU
> to a 1-bit serial flash (AT45DB161D).
>
> Flash side: 4096*1
> CPU =A0 side: 256*16 (512 bytes)
>
> BRAM X is used to transmit data from CPU to FLASH, and
> BRAM Y from FLASH to CPU.
>
> I've connected the CPU data bus like this:
>
> BRAM X
> DBUS(8) ... DBUS(15), DBUS(0) .. DBUS(7)
>
> BRAM Y
> 8 ... 15, 0 .. 7 (ie. the same)
>
> Both reading and writing works fine.
>
> However, for security reasons,
> I wish to scramble the bus:
>
> BRAM X
> 12, 1, 6, 9, 15, 4, 14, 7, 2, 5, 8, 11, 3, 10, 0, 13.
>
> (all 16 DBUS bits, just not in order)
>
> I presumed the BRAM Y should have the same DBUS
> order, but then reading gets invalid data.
> After some trial and error, I've found the required
> order on the BRAM Y:
>
> 11, 9, 0, 15, 4, 2, 12, 5, 8, 13, 6, 10, 3, 7, 14, 1.
>
> Can anyone explain why is the order of DBUS
> on BRAM X & Y the same in the first case
> and not in the second one?
>
> All buses are std_logic_vector(15 downto 0)

I forgot to mention that the FPGA only
sends/receives DATA block to/from FLASH,
and that the controlling of the FLASH
(sending command and address) is done
by another micro. (not main CPU).

The problem is internal to FPGA
and has nothing to do with FLASH.
(the flash sends back data in the
order it has received it.)

I just don't see why is the order of
DBUS connections different in these two cases..

Take a look at your numbering.  On bram X, bit 15 is connected to bit
11.  On bram Y bit 11 is connected to bit 15.  You don't have a logic
problem, you have a nomenclature problem.  You are permuting the buses
in different ways on the two sides.

Rick

On Apr 10, 1:17=A0pm, aleksa <aleks...@gmail.com> wrote:
> I'm using two dual port BRAMs to connect a 16-bit CPU
> to a 1-bit serial flash (AT45DB161D).
>
> Flash side: 4096*1
> CPU =A0 side: 256*16 (512 bytes)
>
> BRAM X is used to transmit data from CPU to FLASH, and
> BRAM Y from FLASH to CPU.
>
> I've connected the CPU data bus like this:
>
> BRAM X
> DBUS(8) ... DBUS(15), DBUS(0) .. DBUS(7)
>
> BRAM Y
> 8 ... 15, 0 .. 7 (ie. the same)
>
> Both reading and writing works fine.
>
> However, for security reasons,
> I wish to scramble the bus:
>
> BRAM X
> 12, 1, 6, 9, 15, 4, 14, 7, 2, 5, 8, 11, 3, 10, 0, 13.
>
> (all 16 DBUS bits, just not in order)
>
> I presumed the BRAM Y should have the same DBUS
> order, but then reading gets invalid data.
> After some trial and error, I've found the required
> order on the BRAM Y:
>
> 11, 9, 0, 15, 4, 2, 12, 5, 8, 13, 6, 10, 3, 7, 14, 1.
>
> Can anyone explain why is the order of DBUS
> on BRAM X & Y the same in the first case
> and not in the second one?
>
> All buses are std_logic_vector(15 downto 0)

umm...

You realize you need to do the reverse function
for the return data?

i.e. for the first case you have:
0 -- 0
1 -- 1
2 -- 2
. . .
15 -- 15

so of course the reverse function is the same as the
original.

Now you have:
12 -- 15
 1 -- 14
 6 -- 13
 9 -- 12
15 -- 11
 4 -- 10
14 --  9
 7 --  8
 2 --  7
 5 --  6
 8 --  5
11 --  4
 3 --  3
10 --  2
 0 --  1
13 -- 0

So using the numbers on the left to find the bit you
want on the right gives you

15 -- 11
14 --  9
13 --  0
12 -- 15
11 --  4
10 --  2
 9 -- 12
 8 --  5
 7 --  8
 6 -- 13
 5 --  6
 4 -- 10
 3 --  3
 2 --  7
 1 -- 14
 0 --  1

by simply sorting the table using the left column.

Regards,
Gabor

On Apr 10, 10:13=A0pm, rickman <gnu...@gmail.com> wrote:
> Take a look at your numbering. =A0On bram X, bit 15 is connected to bit
> 11. =A0On bram Y bit 11 is connected to bit 15. =A0You don't have a logic
> problem, you have a nomenclature problem. =A0You are permuting the buses
> in different ways on the two sides.
>
> Rick

Rick, thank you very much, I get it now.

On Apr 10, 10:20=A0pm, gabor <ga...@alacron.com> wrote:
> On Apr 10, 1:17=A0pm, aleksa <aleks...@gmail.com> wrote:
>
>
>
>
>
> > I'm using two dual port BRAMs to connect a 16-bit CPU
> > to a 1-bit serial flash (AT45DB161D).
>
> > Flash side: 4096*1
> > CPU =A0 side: 256*16 (512 bytes)
>
> > BRAM X is used to transmit data from CPU to FLASH, and
> > BRAM Y from FLASH to CPU.
>
> > I've connected the CPU data bus like this:
>
> > BRAM X
> > DBUS(8) ... DBUS(15), DBUS(0) .. DBUS(7)
>
> > BRAM Y
> > 8 ... 15, 0 .. 7 (ie. the same)
>
> > Both reading and writing works fine.
>
> > However, for security reasons,
> > I wish to scramble the bus:
>
> > BRAM X
> > 12, 1, 6, 9, 15, 4, 14, 7, 2, 5, 8, 11, 3, 10, 0, 13.
>
> > (all 16 DBUS bits, just not in order)
>
> > I presumed the BRAM Y should have the same DBUS
> > order, but then reading gets invalid data.
> > After some trial and error, I've found the required
> > order on the BRAM Y:
>
> > 11, 9, 0, 15, 4, 2, 12, 5, 8, 13, 6, 10, 3, 7, 14, 1.
>
> > Can anyone explain why is the order of DBUS
> > on BRAM X & Y the same in the first case
> > and not in the second one?
>
> > All buses are std_logic_vector(15 downto 0)
>
> umm...
>
> You realize you need to do the reverse function
> for the return data?

I didn't realize that..

The one-to-one order in the first sample
made me believe that it is really simple!


>
> i.e. for the first case you have:
> 0 -- 0
> 1 -- 1
> 2 -- 2
> . . .
> 15 -- 15
>
> so of course the reverse function is the same as the
> original.
>
> Now you have:
> 12 -- 15
> =A01 -- 14
> =A06 -- 13
> =A09 -- 12
> 15 -- 11
> =A04 -- 10
> 14 -- =A09
> =A07 -- =A08
> =A02 -- =A07
> =A05 -- =A06
> =A08 -- =A05
> 11 -- =A04
> =A03 -- =A03
> 10 -- =A02
> =A00 -- =A01
> 13 -- 0
>
> So using the numbers on the left to find the bit you
> want on the right gives you
>
> 15 -- 11
> 14 -- =A09
> 13 -- =A00
> 12 -- 15
> 11 -- =A04
> 10 -- =A02
> =A09 -- 12
> =A08 -- =A05
> =A07 -- =A08
> =A06 -- 13
> =A05 -- =A06
> =A04 -- 10
> =A03 -- =A03
> =A02 -- =A07
> =A01 -- 14
> =A00 -- =A01
>
> by simply sorting the table using the left column.
>
> Regards,
> Gabor- Hide quoted text -
>
> - Show quoted text -

Thank you for the sort idea