How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex 4 LX 60)

Hi everybody,

in my design i have a timing problem with an ADC. I have this problem
since my design has become more dense:
This is the ADC I'm using: AD677 (http://www.analog.com/static/
imported-files/data_sheets/AD677.pdf)

My ADC-Entity has 3 inputs and 3 outputs. (see datasheet)

BUSY: IN
SCLK: IN
SDATA: IN

CAL: OUT
CLK: OUT
SAMPLE: OUT

How do i now define the relationship between the CLK-output and the
SCLK-input for example? In the datasheet are the timing-
specifications.

Abstract of my *.UCF file:

NET	ADC1_BUSY	LOC	=	C25;
NET	ADC1_SCLK	LOC	=	E24;
NET	ADC1_SDATA	LOC	=	B24;

NET	ADC1_CAL	LOC	=	E14;
NET	ADC1_CLK	LOC	=	D11;
NET "ADC1_SAMPLE" LOC = F14;


I hope somebody with some experience in constraining a design can give
me some hints.
The only timing constraint i'm using right now is the period
constraint for the 100 MHz-clock i'm using.
I'm an absolute beginner in timing-constraint.... In advance thanks a
lof for your help.

sincerely yours

Olli





Here the whole UCF-File:

CONFIG STEPPING = "2";


NET	clk			LOC	=	B13;

NET	ADC_reset	LOC	=	G9;
NET	ADC1_BUSY	LOC	=	C25;
NET	ADC1_CAL	LOC	=	E14;
NET	ADC1_CLK	LOC	=	D11;
NET	ADC1_SCLK	LOC	=	E24;
NET	ADC1_SDATA	LOC	=	B24;
NET	ADC2_BUSY	LOC	=	F24;
NET	ADC2_CAL	LOC	=	D13;
NET	ADC2_CLK	LOC	=	D14;
NET	ADC2_SAMPLE	LOC	=	C11;
NET	ADC2_SCLK	LOC	=	C26;
NET	ADC2_SDATA	LOC	=	E23;


NET	DEACTIVATE_N	LOC	=	N25;
NET	MESS_DONE		LOC	=	L26;
NET	MESS_ENABLE		LOC	=	E2;
NET	M_RESET			LOC	=	E1;

NET	DIP_STRING		LOC	=	A4;
NET	DIP_TD_READMODE	LOC	=	B6;
NET	DOUT			LOC	=	C24;

NET	Druck_VCC		LOC	=	F11;
NET	DIN				LOC	=	A23;
NET	MCLK			LOC	=	F16;
NET	SCLK	LOC	=	B23;

NET	MITTLUNG_LED	LOC	=	V25;
NET	MITTLUNG0		LOC	=	B4;
NET	MITTLUNG1		LOC	=	C6;

NET	modell_MESSUNG	LOC	=	G10;


NET	SER_IN_0	LOC	=	U4;
NET	SER_IN_1	LOC	=	AA11;
NET	SER_OUT_0	LOC	=	V4;
NET	SER_OUT_1	LOC	=	AC11;
NET "SER_OUT_2" LOC = AC15;
NET "SER_IN_2" LOC = AC14;
NET	SHIFT_5_TO_3<7>	LOC	=	AC12;
NET	SHIFT_5_TO_3<6>	LOC	=	AA13;
NET	SHIFT_5_TO_3<5>	LOC	=	AD13;
NET	SHIFT_5_TO_3<4>	LOC	=	AB13;
NET	SHIFT_5_TO_3<3>	LOC	=	AC13;
NET	SHIFT_5_TO_3<2>	LOC	=	AA14;
NET	SHIFT_5_TO_3<1>	LOC	=	AD14;
NET	SHIFT_5_TO_3<0>	LOC	=	AB14;
NET	TASTER1	LOC	=	D2;
NET	TASTER2	LOC	=	D1;
NET	TD_out	LOC	=	F12;
NET	TD_out2	LOC	=	F13;
NET	TD_VCC	LOC	=	D16;
NET	TD_VCC2	LOC	=	D15;
NET	URX_LED	LOC	=	K26;
NET	URX_TX_go_to	LOC	=	C10;
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 10 ns;
NET "mittlung_LED" LOC = V25;
NET "ADC1_SAMPLE" LOC = F14;
NET "EIN_kHZ" LOC = AA15;




NET "EIN_kHz" LOC = AA15;
NET "pin_x" LOC = AD25;
NET "pin_y" LOC = AC19;
NET "pin_z" LOC = AD19;
NET "sync" LOC = AC16;
NET "sendclk" LOC = AA16;

On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com"
<oliver.hofh...@googlemail.com> wrote:
> Hi everybody,
>
> in my design i have a timing problem with an ADC. I have this problem
> since my design has become more dense:
> This is the ADC I'm using: AD677 (http://www.analog.com/static/
> imported-files/data_sheets/AD677.pdf)
>
> My ADC-Entity has 3 inputs and 3 outputs. (see datasheet)
>
> BUSY: IN
> SCLK: IN
> SDATA: IN
>
> CAL: OUT
> CLK: OUT
> SAMPLE: OUT
>
> How do i now define the relationship between the CLK-output and the
> SCLK-input for example? In the datasheet are the timing-
> specifications.
>
> Abstract of my *.UCF file:
>
> NET =A0 =A0 ADC1_BUSY =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 C25;
> NET =A0 =A0 ADC1_SCLK =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 E24;
> NET =A0 =A0 ADC1_SDATA =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 B24;
>
> NET =A0 =A0 ADC1_CAL =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 E14;
> NET =A0 =A0 ADC1_CLK =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 D11;
> NET "ADC1_SAMPLE" LOC =3D F14;
>
> I hope somebody with some experience in constraining a design can give
> me some hints.
> The only timing constraint i'm using right now is the period
> constraint for the 100 MHz-clock i'm using.
> I'm an absolute beginner in timing-constraint.... In advance thanks a
> lof for your help.
>
> sincerely yours
>
> Olli
>
> Here the whole UCF-File:
>
> CONFIG STEPPING =3D "2";
>
> NET =A0 =A0 clk =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =
=A0 =A0 =A0 B13;
>
> NET =A0 =A0 ADC_reset =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 G9;
> NET =A0 =A0 ADC1_BUSY =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 C25;
> NET =A0 =A0 ADC1_CAL =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 E14;
> NET =A0 =A0 ADC1_CLK =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 D11;
> NET =A0 =A0 ADC1_SCLK =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 E24;
> NET =A0 =A0 ADC1_SDATA =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 B24;
> NET =A0 =A0 ADC2_BUSY =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 F24;
> NET =A0 =A0 ADC2_CAL =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 D13;
> NET =A0 =A0 ADC2_CLK =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 D14;
> NET =A0 =A0 ADC2_SAMPLE =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 C11;
> NET =A0 =A0 ADC2_SCLK =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 C26;
> NET =A0 =A0 ADC2_SDATA =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 E23;
>
> NET =A0 =A0 DEACTIVATE_N =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 N25;
> NET =A0 =A0 MESS_DONE =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0=
 =A0 L26;
> NET =A0 =A0 MESS_ENABLE =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =
=A0 E2;
> NET =A0 =A0 M_RESET =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =
=A0 =A0 E1;
>
> NET =A0 =A0 DIP_STRING =A0 =A0 =A0 =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0=
 =A0 A4;
> NET =A0 =A0 DIP_TD_READMODE LOC =A0 =A0 =3D =A0 =A0 =A0 B6;
> NET =A0 =A0 DOUT =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =
=A0 =A0 =A0 C24;
>
> NET =A0 =A0 Druck_VCC =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0=
 =A0 F11;
> NET =A0 =A0 DIN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 L=
OC =A0 =A0 =3D =A0 =A0 =A0 A23;
> NET =A0 =A0 MCLK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =
=A0 =A0 =A0 F16;
> NET =A0 =A0 SCLK =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 B23;
>
> NET =A0 =A0 MITTLUNG_LED =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 V25;
> NET =A0 =A0 MITTLUNG0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0=
 =A0 B4;
> NET =A0 =A0 MITTLUNG1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0=
 =A0 C6;
>
> NET =A0 =A0 modell_MESSUNG =A0LOC =A0 =A0 =3D =A0 =A0 =A0 G10;
>
> NET =A0 =A0 SER_IN_0 =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 U4;
> NET =A0 =A0 SER_IN_1 =A0 =A0 =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 AA11;
> NET =A0 =A0 SER_OUT_0 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 V4;
> NET =A0 =A0 SER_OUT_1 =A0 =A0 =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AC11;
> NET "SER_OUT_2" LOC =3D AC15;
> NET "SER_IN_2" LOC =3D AC14;
> NET =A0 =A0 SHIFT_5_TO_3<7> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AC12;
> NET =A0 =A0 SHIFT_5_TO_3<6> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AA13;
> NET =A0 =A0 SHIFT_5_TO_3<5> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AD13;
> NET =A0 =A0 SHIFT_5_TO_3<4> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AB13;
> NET =A0 =A0 SHIFT_5_TO_3<3> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AC13;
> NET =A0 =A0 SHIFT_5_TO_3<2> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AA14;
> NET =A0 =A0 SHIFT_5_TO_3<1> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AD14;
> NET =A0 =A0 SHIFT_5_TO_3<0> =A0 LOC =A0 =A0 =3D =A0 =A0 =A0 AB14;
> NET =A0 =A0 TASTER1 LOC =A0 =A0 =3D =A0 =A0 =A0 D2;
> NET =A0 =A0 TASTER2 LOC =A0 =A0 =3D =A0 =A0 =A0 D1;
> NET =A0 =A0 TD_out =A0LOC =A0 =A0 =3D =A0 =A0 =A0 F12;
> NET =A0 =A0 TD_out2 LOC =A0 =A0 =3D =A0 =A0 =A0 F13;
> NET =A0 =A0 TD_VCC =A0LOC =A0 =A0 =3D =A0 =A0 =A0 D16;
> NET =A0 =A0 TD_VCC2 LOC =A0 =A0 =3D =A0 =A0 =A0 D15;
> NET =A0 =A0 URX_LED LOC =A0 =A0 =3D =A0 =A0 =A0 K26;
> NET =A0 =A0 URX_TX_go_to =A0 =A0LOC =A0 =A0 =3D =A0 =A0 =A0 C10;
> NET "clk" TNM_NET =3D clk;
> TIMESPEC TS_clk =3D PERIOD "clk" 10 ns;
> NET "mittlung_LED" LOC =3D V25;
> NET "ADC1_SAMPLE" LOC =3D F14;
> NET "EIN_kHZ" LOC =3D AA15;
>
> NET "EIN_kHz" LOC =3D AA15;
> NET "pin_x" LOC =3D AD25;
> NET "pin_y" LOC =3D AC19;
> NET "pin_z" LOC =3D AD19;
> NET "sync" LOC =3D AC16;
> NET "sendclk" LOC =3D AA16;

There is no relationship. I think clk and sclk are essentially
asynchronous to each other as seen from the FPGA since you can't be
sure of the delay on the board for each signal.

On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com"
<oliver.hofh...@googlemail.com> wrote:
> Hi everybody,
>
> in my design i have a timing problem with an ADC. I have this problem
> since my design has become more dense:
> [...]
> How do i now define the relationship between the CLK-output and the
> SCLK-input for example? In the datasheet are the timing-
> specifications.
>

CLK to SCLK varies from 100 to 300 ns. Your clock has a period of
10ns, so I am not sure what you want to accomplish with timing
constraints. How do you communicate with the ADC?

-Mike

On 17 Apr., 00:20, mng <michael.jh...@gmail.com> wrote:
> On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com"
>
> <oliver.hofh...@googlemail.com> wrote:
> > Hi everybody,
>
> > in my design i have a timing problem with an ADC. I have this problem
> > since my design has become more dense:
> > [...]
> > How do i now define the relationship between the CLK-output and the
> > SCLK-input for example? In the datasheet are the timing-
> > specifications.
>
> CLK to SCLK varies from 100 to 300 ns. Your clock has a period of
> 10ns, so I am not sure what you want to accomplish with timing
> constraints. How do you communicate with the ADC?
>
> -Mike

Hi, the ADC is directly connected to the FPGA-Pins. The communication
is realized with a state machine that runs in the fpga.

On Apr 17, 5:44=A0am, olliH <oliver.hofh...@googlemail.com> wrote:
> On 17 Apr., 00:20, mng <michael.jh...@gmail.com> wrote:
>
>
>
> > On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com"
>
> > <oliver.hofh...@googlemail.com> wrote:
> > > Hi everybody,
>
> > > in my design i have a timing problem with an ADC. I have this problem
> > > since my design has become more dense:
> > > [...]
> > > How do i now define the relationship between the CLK-output and the
> > > SCLK-input for example? In the datasheet are the timing-
> > > specifications.
>
> > CLK to SCLK varies from 100 to 300 ns. Your clock has a period of
> > 10ns, so I am not sure what you want to accomplish with timing
> > constraints. How do you communicate with the ADC?
>
> > -Mike
>
> Hi, the ADC is directly connected to the FPGA-Pins. The communication
> is realized with a state machine that runs in the fpga.

The ADC CLK is ~2 MHz or less, and your FPGA runs at 100 MHz. In this
situation I would simply sample SCLK for rising edges -- timing
constraints aren't useful here. If you are trying to do it a different
way, I have no idea what it is, and you will have to provide more
details.

-Mike

On 18 Apr., 02:29, mng <michael.jh...@gmail.com> wrote:
> On Apr 17, 5:44=A0am, olliH <oliver.hofh...@googlemail.com> wrote:
>
>
>
> > On 17 Apr., 00:20, mng <michael.jh...@gmail.com> wrote:
>
> > > On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com"
>
> > > <oliver.hofh...@googlemail.com> wrote:
> > > > Hi everybody,
>
> > > > in my design i have a timing problem with an ADC. I have this probl=
em
> > > > since my design has become more dense:
> > > > [...]
> > > > How do i now define the relationship between the CLK-output and the
> > > > SCLK-input for example? In the datasheet are the timing-
> > > > specifications.
>
> > > CLK to SCLK varies from 100 to 300 ns. Your clock has a period of
> > > 10ns, so I am not sure what you want to accomplish with timing
> > > constraints. How do you communicate with the ADC?
>
> > > -Mike
>
> > Hi, the ADC is directly connected to the FPGA-Pins. The communication
> > is realized with a state machine that runs in the fpga.
>
> The ADC CLK is ~2 MHz or less, and your FPGA runs at 100 MHz. In this
> situation I would simply sample SCLK for rising edges -- timing
> constraints aren't useful here. If you are trying to do it a different
> way, I have no idea what it is, and you will have to provide more
> details.
>
> -Mike

Hi Mike,

thank you for your answer. I just wasn't sure if timing constraints
are necessary or not.

Olli