Fan Out Problem..

Hello FPGA gurus..

I am designing a micro using Quartus II v4.0 and the target FPGA is Flex10K
(EPF10K20RC240-4). I know it's a very outdated FPGA, but that's all I have
:(
The ALU unit when I compile stand along compiles and works as expected.
However when the ALU is combined with the rest of the micro, during
'analysis & synthesis' I get a long list of warning..
..
here is the warning list
-----------
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00040|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00038|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00036|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00034|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00032|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00030|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00028|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00026|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00024|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00022|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00020|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00018|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00016|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00014|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00012|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00010|muxlut:$00018|$00012 contains fan-out
to more than one destination
------------

After this stage, QII crashes and gives the following error (with option to
contact Altera)
----------
Internal Error: Sub-system: FTM, File: ftm_main.cpp, Line: 5851
oterm->get_number_of_fanout() == 1
Quartus II Version 4.0 Build 190 1/28/2004 SJ Full Version
----------

Now I have only one mux in my ALU. All that mux does is decides which result
to put on the output result bux depending on the value of the sel line
(which is decided
in some other module).. The code of the lpm_mux is as follows:
----------
 Gen_2D_Out2 : FOR sig_Cnt IN 0 TO 15 GENERATE
        sig_Output_Array (0, sig_Cnt) <= sig_ALU_AddSub_IncDec_Result
(sig_Cnt);
  sig_Output_Array (1, sig_Cnt) <= sig_ALU_AND_Result (sig_Cnt);
  sig_Output_Array (2, sig_Cnt) <= sig_ALU_NAND_Result (sig_Cnt);
  sig_Output_Array (3, sig_Cnt) <= sig_ALU_OR_Result (sig_Cnt);
  sig_Output_Array (4, sig_Cnt) <= sig_ALU_XOR_Result (sig_Cnt);
  sig_Output_Array (5, sig_Cnt) <= sig_ALU_Abs_Result (sig_Cnt);
  sig_Output_Array (6, sig_Cnt) <= sig_ALU_MpyH_Result (sig_Cnt);
  sig_Output_Array (7, sig_Cnt) <= sig_ALU_MpyL_Result (sig_Cnt);
  sig_Output_Array (8, sig_Cnt) <= sig_ALU_LogicalShift_Result (sig_Cnt);
  sig_Output_Array (9, sig_Cnt) <= sig_ALU_RotateShift_Result (sig_Cnt);
  sig_Output_Array (10, sig_Cnt) <= sig_ALU_Divide_Result (sig_Cnt);
 END GENERATE;

 Mux : lpm_mux
  GENERIC map (
      LPM_WIDTH  => 16,
      LPM_SIZE  => 11,
      LPM_WIDTHS  => 4,
      LPM_PIPELINE => 0,
      LPM_TYPE  => "LPM_MUX",
      LPM_HINT  => "UNUSED"
     )
  PORT map (
      data   => sig_Output_Array,
      --aclr   => ,
      --clock   => ,
      sel    => ALU_Result_Mux,
      result   => ALU_Result
     );
----------

Can someone pls help me with this problem..
Thanks in advance