Dual-frequency quartz oscillator with a FPGA ?

Hello,

this is with great emotion that I am designing my first FPGA board.
However, the clock frequency that I desire is only available as
a discrete quartz, not oscillator (and integrated oscillators are more expensive).
And I don't find a dedicated quartz input in the chips I use
(the eval boards all use integrated oscillators).
There is no way I can use the PLL to get the desired frequencies
because the ratio is quite complex and would result in unacceptable drift
(not that it matters now but it's better to do things correctly
from the beginning, and now is the best time since it's a first draft).

So I have to make a quartz oscillator circuit and it would use the
FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
with 18pF capacitors to the ground and a series resistor (1K Ohm)
that limits the current in the quartz (I have seen other values as well).
I could use an external single not gate to reduce the chance of
parasitic pickup but I would like to keep the circuit simple now
and drift is more annoying than jitter, since a PLL will generate
higher frequencies and this will be filtered.

In VHDL this amounts to something like

  OSC_out <= not( OSC_in ) and OSC_EN;
  PLL_in <= OSC_in;

* OSC_out would be in low drive configuration (like 2mA)
with a series resistor.

* OSC_in would be tied to a pin that connects directly to the PLL
   and/or the internal clock network.


I also need to select one quartz among 2 as a source for the
base clock. I would like to connect the 2 quartz with a common OSC_in pin,
while each quartz has a dedicated OSC_outX pin.
This is the simplest idea I can find, with a relatively benign
transition mechanism : only the transition signal has to be
synchronised (a couple of D latches), instead of having 2 separate
clocks that must run simultaneously.
It also avoids a 4-register "glitch-free switch"
(see http://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitchfree.html )
and the transition does not create a dramatic phase change.
I even wonder what would happen if the 2 quartz are
temporarily used in parallel (so the new quartz will start up a few
cycles before transition). Note that frequency changes should
not occur often and the frequencies are only 10% apart.

OSC_out1 <= not( OSC_in ) if ( OSC_en1 == '1' ) else 'Z'
OSC_out2 <= not( OSC_in ) if ( OSC_en2 == '1' ) else 'Z'

===> OSC_en1 and OSC_en2 could overlap during a few cycles

Did I miss something ? Do I forget any trap with quartz oscillators
and FPGAs ? Does the routing in the FPGA fabric play a big role
(considering a frequency in the 10MHz range) ? How can I be sure
that the oscillator will start up and switch correctly ?
How many cycles should the frequency overlap last ?
Is there a better method ?
Has anybody done this, and what are the results ?

Thank you for sharing your thoughts,
yg

-- 
http://ygdes.com / http://yasep.org

On Apr 18, 2:03=A0am, whygee <why...@yg.yg> wrote:
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more ex=
pensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
> =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> =A0 PLL_in <=3D OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
> =A0 =A0and/or the internal clock network.
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin=
,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-sw=
...)
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> --http://ygdes.com/http://yasep.org

I have tried chrystal drive with Xilinx spartan-3A, and failed - it
did not work reliable
- if you look at msgs here, then Xilinx is keep saying it is NOT
DOABLE..

OTOH Lattice say they do this XP devices

so please test the circuit that it really works as reliable as needed
the xilinx oscillator had startup problems, and I never got it
starting
reliable with correct frequency

Antti

On Apr 17, 4:03=A0pm, whygee <why...@yg.yg> wrote:
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more ex=
pensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
> =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> =A0 PLL_in <=3D OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
> =A0 =A0and/or the internal clock network.
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin=
,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-sw=
...)
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> --http://ygdes.com/http://yasep.org

To build a reliable xtal oscillator, you need a single-stage inverting
amplifier with moderate gain and moderate roll-off (phase response) at
high frequency.
Using an FPGA input + output loop, you get a multi-stage amplifier
with enormous gain, poor phase response, plus hysteresis.
That does not give you an oscillator that starts reliably under all
circumstances.
Buy a canned oscillator, manufactured by people who know this
business.
Last time we at Xilinx offered a specialized single-stage oscillator-
amplifier was in the XC3000 family, 20 years ago. And it still gave us
headaches under extreme conditions ( 32 kHz, high temp, low temp, etc)
Peter Alfke
Peter Alfke

On Apr 18, 9:20=A0am, Peter Alfke <al...@sbcglobal.net> wrote:
> On Apr 17, 4:03=A0pm, whygee <why...@yg.yg> wrote:
>
>
>
>
>
> > Hello,
>
> > this is with great emotion that I am designing my first FPGA board.
> > However, the clock frequency that I desire is only available as
> > a discrete quartz, not oscillator (and integrated oscillators are more =
expensive).
> > And I don't find a dedicated quartz input in the chips I use
> > (the eval boards all use integrated oscillators).
> > There is no way I can use the PLL to get the desired frequencies
> > because the ratio is quite complex and would result in unacceptable dri=
ft
> > (not that it matters now but it's better to do things correctly
> > from the beginning, and now is the best time since it's a first draft).
>
> > So I have to make a quartz oscillator circuit and it would use the
> > FPGA I/Os. To the best of my knowledge, this is a "simple inverting gat=
e"
> > with 18pF capacitors to the ground and a series resistor (1K Ohm)
> > that limits the current in the quartz (I have seen other values as well=
).
> > I could use an external single not gate to reduce the chance of
> > parasitic pickup but I would like to keep the circuit simple now
> > and drift is more annoying than jitter, since a PLL will generate
> > higher frequencies and this will be filtered.
>
> > In VHDL this amounts to something like
>
> > =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> > =A0 PLL_in <=3D OSC_in;
>
> > * OSC_out would be in low drive configuration (like 2mA)
> > with a series resistor.
>
> > * OSC_in would be tied to a pin that connects directly to the PLL
> > =A0 =A0and/or the internal clock network.
>
> > I also need to select one quartz among 2 as a source for the
> > base clock. I would like to connect the 2 quartz with a common OSC_in p=
in,
> > while each quartz has a dedicated OSC_outX pin.
> > This is the simplest idea I can find, with a relatively benign
> > transition mechanism : only the transition signal has to be
> > synchronised (a couple of D latches), instead of having 2 separate
> > clocks that must run simultaneously.
> > It also avoids a 4-register "glitch-free switch"
> > (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-=
sw...)
> > and the transition does not create a dramatic phase change.
> > I even wonder what would happen if the 2 quartz are
> > temporarily used in parallel (so the new quartz will start up a few
> > cycles before transition). Note that frequency changes should
> > not occur often and the frequencies are only 10% apart.
>
> > OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> > OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> > =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> > Did I miss something ? Do I forget any trap with quartz oscillators
> > and FPGAs ? Does the routing in the FPGA fabric play a big role
> > (considering a frequency in the 10MHz range) ? How can I be sure
> > that the oscillator will start up and switch correctly ?
> > How many cycles should the frequency overlap last ?
> > Is there a better method ?
> > Has anybody done this, and what are the results ?
>
> > Thank you for sharing your thoughts,
> > yg
>
> > --http://ygdes.com/http://yasep.org
>
> To build a reliable xtal oscillator, you need a single-stage inverting
> amplifier with moderate gain and moderate roll-off (phase response) at
> high frequency.
> Using an FPGA input + output loop, you get a multi-stage amplifier
> with enormous gain, poor phase response, plus hysteresis.
> That does not give you an oscillator that starts reliably under all
> circumstances.
> Buy a canned oscillator, manufactured by people who know this
> business.
> Last time we at Xilinx offered a specialized single-stage oscillator-
> amplifier was in the XC3000 family, 20 years ago. And it still gave us
> headaches under extreme conditions ( 32 kHz, high temp, low temp, etc)
> Peter Alfke
> Peter Alfke- Hide quoted text -
>
> - Show quoted text -

Peter

the issue is that canned oscillators are not available for all
frequencies,
and sometimes the on chip clock can not be used to generate the
required frequency.

I assume the OP is targetting Actel FPGA not Xilinx part. Well the
basics still apply
so I would also suggest canned oscillator, and

actel PLL can work in frequency dither mode where user circuitry is
connected into
feedback loop, this allows pretty much any frequency to be generated
and switched
on the fly as well

actel app note is for proasic, but it would work on pa3 as well, but a
pin to pin
loopback wire is required because of clock routing restrictions

similar technic was also used by Ken Chapman for S3E, again there is
no
ready made solution for S3A, but after some experiments i have
succeeded
with S3A also. S6 has PLL already... but i think OP needs solution now
and not 2011

Antti

On Apr 18, 2:03=A0am, whygee <why...@yg.yg> wrote:
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more ex=
pensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
> =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> =A0 PLL_in <=3D OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
> =A0 =A0and/or the internal clock network.
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin=
,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-sw=
...)
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> --http://ygdes.com/http://yasep.org

actel Fusion has crhystal osc support, but only for one chrystal

Antti

Thank you for the useful answers :-)

Antti.Lukats@googlemail.com wrote:
> actel Fusion has crhystal osc support, but only for one chrystal

The fusion osc is meant for a 32768Hz Xtal, not the 10MHz range
(I should check though) and I target the A3P125-250 type
(that's much cheaper... and i'll look at the analog stuff later)


> Antti
yg

-- 
http://ygdes.com / http://yasep.org

On Apr 18, 11:03=A0am, whygee <why...@yg.yg> wrote:
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?

As others have said, unreliable and risky.,

If you want Xtal operation, use something like TinyLogic 74LVC1GX04
crystal oscillator
or, use 74LVC2GU04

Oscillators have a startup time, so you may prefer to run them all the
time, and
switch inside the FPGA.

-jg

"whygee" <whygee@yg.yg> wrote in message 
news:49e90f52$0$21740$7a628cd7@news.club-internet.fr...
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more 
> expensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
>  OSC_out <= not( OSC_in ) and OSC_EN;
>  PLL_in <= OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
>   and/or the internal clock network.
>
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (see 
> http://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitchfree.html )
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <= not( OSC_in ) if ( OSC_en1 == '1' ) else 'Z'
> OSC_out2 <= not( OSC_in ) if ( OSC_en2 == '1' ) else 'Z'
>
> ===> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> -- 
> http://ygdes.com / http://yasep.org

What exact frequencies do you need?

Canned oscillators are made to order by several crystal vendors.

Or, use external single unbuffered CMOS inverter gates e.g. SN74AHC1GU04.

You forgot to mention the feedback resistor which biases the gate into its 
linear region.  This works best with a single gate, not multiple stages as 
you would inevitably have going on and off an FPGA.  There's too much gain. 
It just can't hold them all at 0.5*VDD.  Even if it starts, it may not 
oscillate on the crystal frequency!

You did mention the series current limiting resistor, which is a good idea 
BTW and 1k is a good ballpark value for this.  The feedback resistor can be 
220k - 1M.  The capacitors are chosen to suit the crystal.

Hello again.

Here are some other answers that overlap with other posts.

-jg wrote:
> As others have said, unreliable and risky.,
I was not sure but Peter Alfke gave good arguments why.
I forgot about the gain/phase things...

I have also experienced a reverse situation with a PIC,
which did not work with a canned oscillator, but everything
was fine with a cristal... I still wonder why.

> If you want Xtal operation, use something like TinyLogic 74LVC1GX04
> crystal oscillator or, use 74LVC2GU04
I'm checking this too.

I've also found a working example's schematic using a couple of 74HC14 gates,
two 1M resistors and the usual couple of capacitors...
and I wonder again why a couple of FPGA pins wouldn't work :-/

> Oscillators have a startup time,
I know that this time depends on the capacitors too.

> so you may prefer to run them all the
> time, and switch inside the FPGA.
This means continuous power draw...
even a few mA can matter, not for the proto but in the end... :-/
I'll probably switch to the Igloo family later, too.

It looks like i'll have to choose one fixed frequency
and give up the others, or i'll have to end up with 3 or 4
Xtal operating  simultaneously...
Fortunately, FPGAs have integrated PLLs today.

> -jg
yg

-- 
http://ygdes.com / http://yasep.org

On cost the new MEMS oscillators very often compete well with
crystals. If you are worried about the power why not control the
oscillator power with a mosfet and simply turn it off when not in use.
There a lot of the newer MEMS oscillators that don't use mush power
and are physically very small. Spot the 25MHz MEMs oscillator on here
http://www.enterpoint.co.uk/component_replacements/craignell2.html and
that's not the smallest one we are using.

John Adair
Enterpoint Ltd.

On 18 Apr, 10:42, whygee <why...@yg.yg> wrote:
> Hello again.
>
> Here are some other answers that overlap with other posts.
>
> -jg wrote:
> > As others have said, unreliable and risky.,
>
> I was not sure but Peter Alfke gave good arguments why.
> I forgot about the gain/phase things...
>
> I have also experienced a reverse situation with a PIC,
> which did not work with a canned oscillator, but everything
> was fine with a cristal... I still wonder why.
>
> > If you want Xtal operation, use something like TinyLogic 74LVC1GX04
> > crystal oscillator or, use 74LVC2GU04
>
> I'm checking this too.
>
> I've also found a working example's schematic using a couple of 74HC14 ga=
tes,
> two 1M resistors and the usual couple of capacitors...
> and I wonder again why a couple of FPGA pins wouldn't work :-/
>
> > Oscillators have a startup time,
>
> I know that this time depends on the capacitors too.
>
> > so you may prefer to run them all the
> > time, and switch inside the FPGA.
>
> This means continuous power draw...
> even a few mA can matter, not for the proto but in the end... :-/
> I'll probably switch to the Igloo family later, too.
>
> It looks like i'll have to choose one fixed frequency
> and give up the others, or i'll have to end up with 3 or 4
> Xtal operating =A0simultaneously...
> Fortunately, FPGAs have integrated PLLs today.
>
> > -jg
>
> yg
>
> --http://ygdes.com/http://yasep.org