Dual-frequency quartz oscillator with a FPGA ?

-jg wrote:
<an excellent post that I'm not able to fully digest at this time of writing)

>> But what about the "enable" input of the canned oscillators ?
>> Normally, the osc's output is tristated so (taking into account
>> various capacitances) two oscs should be able to share a single
>> FPGA input pin (then 2 output pins control the enable pins)...
> Yes, but what is clocking the FPGA, when both are off  ?  ;)
that's simple (TM) :
the FPGA is an Actel Flash-based part so the configuration is "live at power-up"
(as the glossy marketing sheets write). The /RESET pin is held down
up to 200ms after the 3.3V rail has settled (with a TPS3908 or equivalent),
so the quartz have enough time to start oscillating.
The "osc_sels" pins are held down by an internal D-FF with a reset input
(with output logic saying that osc_sel1 <= not osc_sel2 ).
During "normal operation", the internal logic can "write" a specific data
('0' or '1') to the DFF (which switches the source clock).

Note that in the case of dual-source clocking in Actel ProASIC3,
the source should come to one pin only (the pin can be selected
from a certain set but all clocks should go there).
It is better to not implement a MUX in the logic fabric
because this could increase the noise, and the I/O are "wired"
(with EEPROM cells) to go to the logic fabric or to the PLL input
(where the clock signal belongs). The "output enable" provided by
canned oscillators is very useful then. I should add small series
resistors at the osc outputs (100 Ohm ?) in case they get accidentally
asserted at the same time (during transition ?).
Also, I'll add pull-down resistors to prevent accidental assertion
of the oscillators during power-up/down, because the FPGA tristates I/Os
when all power supplies are not nominal so no valid
output would be available during some ms...

Well, a single oscillator looks so simple in comparison...
<think></think>
I have maybe found a solution...


Off-topic : what FPGA family provides an internally-generated /RESET signal
to the logic array ? Those that I know require an externel signal...
Now that I think about this, it sounds curious.
This is probably because most chips work with different I/O-cores-whatever voltages,
but then in a Flash-based FPGA at least, one could eventually program
the tripping voltage of a power supply supervisor.
I guess that the Fusion devices are a bit close to this, but the chip
can examine its own power supply with the ADC which means that the core
must be initialised before...

> -jg
yg

-- 
http://ygdes.com / http://yasep.org

Hi !

Brian Drummond wrote:
> On Sun, 19 Apr 2009 03:08:39 +0200, whygee <whygee@yg.yg> wrote:
>> Brian Drummond wrote:
>>> The other crystal is 12.288MHz then.
>> good guess :-)
>> Now if you have a smart idea about how to switch between them
>> without a glitch... Oh well, when i'll add a video output,
>> i'll need yet another oscillator with another frequency :-/
> I would (a) use external oscillators, as others have suggested, for the same
> reasons. I'd be happy with either modules for simplicity, or something amenable
> to oscillator use, like 74HCU04 in some flavour, if economics demand it.
Now, for me it makes no difference, only the availability of the required
frequency matters.

Yes I have changed my mind again, with the help of yet another trick :
44100 and 48000 have 300 as common divisor
(and I need 256 times this frequency). (44100/300)*(48000/300)=23520
I'll have to divide this by 149 or 160 to obtain the right frequency.
This can be done by dynamically changing the divider ratios.

The Actel PLL has only 7-bit ratios, that is too short
(128<147). There are additional 5-bit dividers that can post-divide.
Now I have to find a frequency in the 5-15 MHz range that satisfies
all these division needs and PLL osc. ranges.

Oh, and this frequency should be available and not too expensive :-/
And when I multiply 256*300*147*160, I get a frequency of more than 1.8GHz
and the PLL's VCO ranges from 24 to 350MHz :-/
Maybe I'll be able to solve this with 2 PLLs or another trick ?

> If you need a glitch free switch you need both oscillators running at once, and
> something like a BUFGMUX or one of Peter Alfke's clever little circuits to
> switch between them.
I've seen this some time ago, and used it already :
http://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitchfree.html

> Incidentally I found I could pull the crystal over about +/-150ppm, and there
> was measurably less phase noise (jitter by another name) from a reputable brand
> of crystal.
> If you're interested to talk more, email...
that's interesting, though my concern is more about long-term stability.
150ppm of drift can add up to a significant delay after a while,
which will desynchronise the system...

>> I'm waiting for ecliptek's answer about a sample request.
>> However, I wonder how i'll be able to solder it in
>> the first prototypes (i'm not at ease with the hot air gun yet).
> Heh. Kapton tape a thermocouple to the top of a board and check out the
> temperature profiles you can get with a 2kw Black&Decker hot air paint stripper
> applied underneath...
Oh, so that tape I recently purchased will be more useful than I thought :-)
The thermocouple and the paint stripper are also already available.

regards,
> - Brian
yg

-- 
http://ygdes.com / http://yasep.org

On Sun, 19 Apr 2009 21:35:12 +0200, whygee <whygee@yg.yg> wrote:

>Hi !
>
>Brian Drummond wrote:
>> On Sun, 19 Apr 2009 03:08:39 +0200, whygee <whygee@yg.yg> wrote:
>>> Brian Drummond wrote:
>>>> The other crystal is 12.288MHz then.
>>> good guess :-)

>Yes I have changed my mind again, with the help of yet another trick :
>44100 and 48000 have 300 as common divisor
>(and I need 256 times this frequency). (44100/300)*(48000/300)=23520
>I'll have to divide this by 149 or 160 to obtain the right frequency.

Sorry, I'd forgotten that one. 
It's 147 not 149, or 7*7*3 if you are restricted in ratios...
versus 8*5*4 for 48kHz.

>The Actel PLL has only 7-bit ratios, that is too short
>(128<147). 

(Unless you can use their factors as above. Which means 2 PLLs.

>Now I have to find a frequency in the 5-15 MHz range that satisfies
>all these division needs and PLL osc. ranges.

7.056 MHz sound about right? :-)

>Maybe I'll be able to solve this with 2 PLLs or another trick ?

The alternative - if you can tolerate a tiny (1-10ppm) frequency error - is to
find a high frequency (but less than 1.8G) that you can divide down to close
approximations to both 12.288 and 11.2896. (I had a program to search for these
once...)

Or if you can live with say 3-5ns jitter on the 11/12MHz clock (but
substantially no jitter at the sample rate) use a 200-300MHz osc (standard freq,
standard module) and a phase accumulator to generate 11/12Mhz. This will be
arbitrarily accurate and reloading the phase increment will switch frequency
without glitches. Jitter will be 1 (optionally 1/2) cycle of the fast osc.

>that's interesting, though my concern is more about long-term stability.
>150ppm of drift can add up to a significant delay after a while,
>which will desynchronise the system...

Long term drift would be at least an order of magnitude less; the pull was
because one mode of operation required a PLL round the crystal to synchronise to
other equipment.

- Brian

Brian Drummond wrote:
> On Sun, 19 Apr 2009 21:35:12 +0200, whygee <whygee@yg.yg> wrote:
>> Yes I have changed my mind again, with the help of yet another trick :
>> 44100 and 48000 have 300 as common divisor
>> (and I need 256 times this frequency). (44100/300)*(48000/300)=23520
>> I'll have to divide this by 149 or 160 to obtain the right frequency.
> Sorry, I'd forgotten that one. 
> It's 147 not 149, or 7*7*3 if you are restricted in ratios...
sorry for the type :-)

> versus 8*5*4 for 48kHz.
yes, I wrote them all down...

IIRC the 44100Hz sampling rate comes from a storage medium that used
video tapes, they simply reused the same sampling rate when they designed
the CD standard, because there was no other digital recording equipment
that could match the CD quality... So one should find television
frequencies, divisors or factors, no ?

>> The Actel PLL has only 7-bit ratios, that is too short (128<147). 
> (Unless you can use their factors as above. Which means 2 PLLs.
I'll look at the recent "Igloo plus" or "Igloo E" that have 2 to 6 PLLs.
Currently (for my first custom board) I keep the usual ProASIC3,
cheaper, available and more-or-less compatible with the successors.


>> Now I have to find a frequency in the 5-15 MHz range that satisfies
>> all these division needs and PLL osc. ranges.
> 7.056 MHz sound about right? :-)
sure :-)
I've seen this frequency when playing with the ratios,
but i did not settle there because I needed another *256 factor.
I'll look more closely to this one...

>> Maybe I'll be able to solve this with 2 PLLs or another trick ?
> The alternative - if you can tolerate a tiny (1-10ppm) frequency error - is to
> find a high frequency (but less than 1.8G) that you can divide down to close
> approximations to both 12.288 and 11.2896. (I had a program to search for these
> once...)
hmmm...
If I was OK then I would not bother and use Wolfson or Texas Instruments
chips, they generate "something close enough to the required frequency"
from a 12MHz quartz (that is required by the USB protocol).
I'm not an "audiophile" but I know digital sound enough to know how
to avoid stupid problems later (even when it means that I have to solve
not-so-easy problems now).

> Or if you can live with say 3-5ns jitter on the 11/12MHz clock (but
> substantially no jitter at the sample rate)
yes because it is integrated by the *256 oversampling D/A
(and hopefully a PLL ?)

> use a 200-300MHz osc (standard freq,
> standard module) and a phase accumulator to generate 11/12Mhz.
It's going to buuuuurn power :-/

> This will be
> arbitrarily accurate and reloading the phase increment will switch frequency
> without glitches. Jitter will be 1 (optionally 1/2) cycle of the fast osc.
hmmm... I prefer the PLL idea because it uses special gates, not
those from the fabric. And a phase accumulator needs to work at high speed,
but a standard 32-bit adder in ProASIC3 works generally at 60-70MHz max.
And it eats quite a lot of gates.

thank you for the insight,
> - Brian
yg

-- 
http://ygdes.com / http://yasep.org

Antti.Lukats@googlemail.com wrote:
> 1) Actel PLL tolerates customer xx.yy divider clock remover in the
> feedback loop, so it can generate almost any frequency - see "pll
> clock dither app note"
I've not heard about it yet... I'll have to find it.

> 2) there is dynamic config mode
yes, I count on this one too :-)
I'll modify my SPI master VHDL code to include the 81-bit
shift register thing.

> so you can connect ext freq to 1 pin, and get all the desired
> frequencies from single PLL
> 
> PS for the clock dither you NEED specific extfb path connecting 2
> actual IOs of the FPGA, on PA it was possible in fabric but PA3
> requires external loopback, this loopback wire is one of the things we
> added on FPGA stamp PCB rev B, just to support the clock dither trick

thanks for the tips !

> Antti
yg

-- 
http://ygdes.com / http://yasep.org

On Apr 20, 2:11=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Sun, 19 Apr 2009 21:35:12 +0200, whygee <why...@yg.yg> wrote:
> >Hi !
>
> >Brian Drummond wrote:
> >> On Sun, 19 Apr 2009 03:08:39 +0200, whygee <why...@yg.yg> wrote:
> >>> Brian Drummond wrote:
> >>>> The other crystal is 12.288MHz then.
> >>> good guess :-)
> >Yes I have changed my mind again, with the help of yet another trick :
> >44100 and 48000 have 300 as common divisor
> >(and I need 256 times this frequency). (44100/300)*(48000/300)=3D23520
> >I'll have to divide this by 149 or 160 to obtain the right frequency.
>
> Sorry, I'd forgotten that one.
> It's 147 not 149, or 7*7*3 if you are restricted in ratios...
> versus 8*5*4 for 48kHz.
>
> >The Actel PLL has only 7-bit ratios, that is too short
> >(128<147).
>
> (Unless you can use their factors as above. Which means 2 PLLs.
>
> >Now I have to find a frequency in the 5-15 MHz range that satisfies
> >all these division needs and PLL osc. ranges.
>
> 7.056 MHz sound about right? :-)
>
> >Maybe I'll be able to solve this with 2 PLLs or another trick ?
>
> The alternative - if you can tolerate a tiny (1-10ppm) frequency error - =
is to
> find a high frequency (but less than 1.8G) that you can divide down to cl=
ose
> approximations to both 12.288 and 11.2896. (I had a program to search for=
 these
> once...)
>
> Or if you can live with say 3-5ns jitter on the 11/12MHz clock (but
> substantially no jitter at the sample rate) use a 200-300MHz osc (standar=
d freq,
> standard module) and a phase accumulator to generate 11/12Mhz. This will =
be
> arbitrarily accurate and reloading the phase increment will switch freque=
ncy
> without glitches. Jitter will be 1 (optionally 1/2) cycle of the fast osc=
.
>
> >that's interesting, though my concern is more about long-term stability.
> >150ppm of drift can add up to a significant delay after a while,
> >which will desynchronise the system...
>
> Long term drift would be at least an order of magnitude less; the pull wa=
s
> because one mode of operation required a PLL round the crystal to synchro=
nise to
> other equipment.
>
> - Brian

1) Actel PLL tolerates customer xx.yy divider clock remover in the
feedback loop, so it can generate almost any frequency - see "pll
clock dither app note"
2) there is dynamic config mode


so you can connect ext freq to 1 pin, and get all the desired
frequencies from single PLL

PS for the clock dither you NEED specific extfb path connecting 2
actual IOs of the FPGA, on PA it was possible in fabric but PA3
requires external loopback, this loopback wire is one of the things we
added on FPGA stamp PCB rev B, just to support the clock dither trick

Antti

whygee <whygee@yg.yg> wrote:
 
> IIRC the 44100Hz sampling rate comes from a storage medium that used
> video tapes, they simply reused the same sampling rate when they designed
> the CD standard, because there was no other digital recording equipment
> that could match the CD quality... So one should find television
> frequencies, divisors or factors, no ?

If I remember the story, it was also so that the video tape
based system could be used to store master tapes for CDs.

My first hard disk, a few years after CDs came out,
was 40MB.  Tape was the only medium with enough storage
capacity for a CD master.

-- glen

On Apr 19, 2:13=A0pm, whygee <why...@yg.yg> wrote:
> -jg wrote:
>
[snip]
> Off-topic : what FPGA family provides an internally-generated /RESET sign=
al
> to the logic array ? Those that I know require an externel signal...
> Now that I think about this, it sounds curious.
> This is probably because most chips work with different I/O-cores-whateve=
r voltages,
> but then in a Flash-based FPGA at least, one could eventually program
> the tripping voltage of a power supply supervisor.
> I guess that the Fusion devices are a bit close to this, but the chip
> can examine its own power supply with the ADC which means that the core
> must be initialised before...
>
> > -jg
>
> yg
>
> --http://ygdes.com/http://yasep.org

Pretty much all SRAM-based FPGA's have internal power-on
reset circuitry to trigger the configuration of the part.
While this reset happens well before the logic is up and
running, the nature of the bitstream load lends itself to
an internal reset in that all of the flip-flops and
(usually) RAM cells are initialized during configuration.
An internal reset can be generated simply by releasing
the logic to a running state.  The normal procedure is
to instantiate a short shift register with an initial
value of all 1's (or all 0's for active low logic) and
then shifting in 0's when the chip starts up.  The output
of the shift register will therefore start up the
rest of the chip a few clocks after configuration
is complete without the need for an external reset
signal.

Regards,
Gabor

gabor wrote:
<snip>

Well... you're right. I'm too architecturally biased...

> The normal procedure is
> to instantiate a short shift register with an initial
> value of all 1's (or all 0's for active low logic) and
> then shifting in 0's when the chip starts up.  The output
> of the shift register will therefore start up the
> rest of the chip a few clocks after configuration
> is complete without the need for an external reset
> signal.

Funny...
Long ago, I was in a digital design class in a university.
The teacher was (is ?) a "all state-machine"-guy.
On the first day of the class, he asked the class how to design
a circuit that would receive a serial bitstream and
toggle a bit when it's finished.
I started to describe a system similar to what you just wrote,
and he almost had a fit (well, he was blunt and dismissive).
He went on to describe "his perfect way of doing this"
with high-level stuffs and (for me) some bloat.
For him, "one hot" systems are evil...

I presume that his bias for state machine could come from
his extensive use of PALs (22V10 and the likes)
and I was already well into the FPGA and full-custom world...
Sea-of-gates have (to me) different constraints.
Anyway, I don't remember a case where I had to use
a "state machine formalism". And I try to avoid these cases
anyway because it relies too much on the tools ...
I've already worked with FSM crunching software but a nice
little clean design looks much better to me :-/

(oops now I realise that it could start a flamewar)

> Regards,
> Gabor
yg

-- 
http://ygdes.com / http://yasep.org

Brian Drummond <brian_drummond@btconnect.com> wrote:
> >Nice board. My issue though is : is your oscillator available
> >in 11.2896MHz frequency, and at what cost ? 

> Heh, thought as much.
> The other crystal is 12.288MHz then.

Curiosity led me to this thread which perhaps might be of interest:

   http://www.diyaudio.com/forums/showthread/t-25921.html

G.