Antti wrote:> Hi_o/ <snip>> japanese mr16 is a small 16 bit RISC with assembler > (aasm-with sources and mr16 support macros) > small soc with mr16+12 16 bit gpout, + timer unit > takes 291 xilinx slices > it might be the nices 16 bit core around...I would enjoy seeing this :-)> Anttiyg -- http://ygdes.com / http://yasep.org
Re: some soft-processors
Started by ●April 24, 2009
Reply by ●April 24, 20092009-04-24
Hi while organizing my past life projects, i refound the NIOX code it is somewhat NIOS-II compatible, vendor neutral verilog xilinx tools say 740 slices if anybody interested to take a look or use-modify it please contact me, I am not sure if i re-release the sources again or not --------------------- 2] japanese mr16 is a small 16 bit RISC with assembler (aasm-with sources and mr16 support macros) small soc with mr16+12 16 bit gpout, + timer unit takes 291 xilinx slices it might be the nices 16 bit core around... Antti
Reply by ●April 24, 20092009-04-24
On Apr 24, 10:27=A0am, whygee <why...@yg.yg> wrote:> Antti wrote: > > Hi > > _o/ > > <snip> > > > japanese mr16 is a small 16 bit RISC with assembler > > (aasm-with sources and mr16 support macros) > > small soc with mr16+12 16 bit gpout, + timer unit > > takes 291 xilinx slices > > it might be the nices 16 bit core around... > > I would enjoy seeing this :-) > > > Antti > > yg > > --http://ygdes.com/http://yasep.orggoogle mr16 verilog take first hit
Reply by ●May 6, 20092009-05-06
> google mr16 verilog > > take first hitI tried this, but it only takes me to a copy of this thread on www.fpgarelated.com. Do you have a permanent link to the project? Best regards, Marc
Reply by ●May 6, 20092009-05-06
On May 6, 1:51=A0pm, jetm...@hotmail.com wrote:> > google mr16 verilog > > > take first hit > > I tried this, but it only takes me to a copy of this thread onwww.fpgarel=ated.com.> > Do you have a permanent link to the project? > > Best regards, > Marchttp://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.html
Reply by ●May 15, 20092009-05-15
On May 6, 8:55=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> http://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.htmlAs brilliant as this may be, everything is in japaneese, the pdfs can't be accessed and the project appears completely unmaintained. Still, in the interest of gauging how hard it would be to compile for, I would like to see an overview of the ISA. Tommy
Reply by ●May 15, 20092009-05-15
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message news:4d9cae4e-e4d8-4c62-8448-8a029071cebb@s1g2000prd.googlegroups.com... On May 6, 8:55 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> http://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.htmlAs brilliant as this may be, everything is in japaneese, the pdfs can't be accessed and the project appears completely unmaintained. Still, in the interest of gauging how hard it would be to compile for, I would like to see an overview of the ISA. =============== http://translate.google.com/translate?sourceid=navclient&hl=en&u=http%3a%2f%2fmembers%2eat%2einfoseek%2eco%2ejp%2fx1resource%2fxilinx%2fip%2fmr16%2fmr16%2ehtml There's a 'Translate page' button on the Google Bar.
Reply by ●May 16, 20092009-05-16
On May 15, 7:39=A0pm, Tommy Thorn <tommy.th...@gmail.com> wrote:> On May 6, 8:55=A0am, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > >http://members.at.infoseek.co.jp/x1resource/xilinx/ip/mr16/mr16.html > > As brilliant as this may be, everything is in japaneese, the pdfs > can't be accessed and the project appears completely unmaintained. > > Still, in the interest of gauging how hard it would be to compile for, > I would like to see an overview of the ISA. > > Tommyeh, i usually dont care if it is japanese or not, as long as there are links to downloadable hdl code the mr16 is used in one japanese RETRO project where it does some system peripheral emulation that project is maintained i think eh, i just found POC(tm) Pascal On Chip IP core it does execute the old pascal-s pseudo codes in hardware only 145 slices :) - without the console opcodes Antti
Reply by ●May 16, 20092009-05-16
On May 16, 6:47=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> eh, i just found POC(tm) Pascal On Chip IP core > > it does execute the old pascal-s pseudo codes in hardware > only 145 slices :) - without the console opcodesAny links for that POC ? Is it a HW version of this ? http://en.wikipedia.org/wiki/P-code_machine#Example_machine or can it run this ? http://www.moorecad.com/standardpascal/pascals.html -jg
Reply by ●May 17, 20092009-05-17
On May 17, 1:16=A0am, -jg <Jim.Granvi...@gmail.com> wrote:> On May 16, 6:47=A0pm, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > > eh, i just found POC(tm) Pascal On Chip IP core > > > it does execute the old pascal-s pseudo codes in hardware > > only 145 slices :) - without the console opcodes > > Any links for that POC ? > > Is it a HW version of this ?http://en.wikipedia.org/wiki/P-code_machine#E=xample_machine> > or can it run this ?http://www.moorecad.com/standardpascal/pascals.html > > -jgi think probably more of the later, I did take some pascal-s compiler and tried to implement it in FPGA I have done this as AVR virtual machine before, was even tested on some AVR boards. the direct FPGA version was optimized for single cycle operation so every clock 24 bits of instruction and 2 16 bit words TOS/NOS are fetched from BRAMs here is list of implemented opcodes (marked with + ) /* from PASCALM.pas + add =3D 0; { opcodes } + neg =3D 1; use T. Coonan verilog muldiv16! mul =3D 2; divd =3D 3; remd =3D 4; + div2 =3D 5; + rem2 =3D 6; check comparison! + eqli =3D 7; + neqi =3D 8; + lssi =3D 9; + leqi =3D 10; + gtri =3D 11; + geqi =3D 12; + dupl =3D 13; + swap =3D 14; check logic ops + andb =3D 15; + orb =3D 16; load =3D 17; stor =3D 18; + hlt =3D 19; { terminate program } + stop =3D 20; { end of code } need a solution for console and streaming? wri =3D 21; * wrc =3D 22; wrl =3D 23; rdi =3D 24; rdc =3D 25; rdl =3D 26; eofi =3D 27; { check eof } eol =3D 28; + ldc =3D 29; lda =3D 30; { load address } ldla =3D 31; ldl =3D 32; ldg =3D 33; stl =3D 34; stg =3D 35; implement as P-Code handler?? move =3D 36; copy =3D 37; + addc =3D 38; mulc =3D 39; + jump =3D 40; + jumpz =3D 41; check call + call =3D 42; + adjs =3D 43; was same as adjs why ?? ++? sets =3D 44; check exit! + exitt =3D 45; */ I was at that focusing in as much as possible single cycle exec, so some op codes are not yet implemented (the hard ones) also probably some opcodes should be emulated by trap and soft handler rather then being full in hw the machine executing the above opcodes is 145 slices but i do not seem to have tested it with real pascal compiled output, only some asm test cases --- I am thinking hard how would be the best way others could benefit the most of what i have done in my life... not yet figured out how :( but thinking process is on Antti
