Spartan3E Starter Kit MISO and Flash pin shared

Hi,

I've been working on a Spartan3E Starter Kit and I've hit a snag while
using both the onboard ADC and the StrataFlash PROM.  The SPI bus MISO
signal for the ADC and the memory's bit0 for its data are the same net. 
Could anyone explain how to map the MISO and data pin to the same NET? 
I've tried doing it in the MHS and UCF files in the Xilinx EDK, but it
doesn't seem to hold.  I think I may need to either modify the VHDL code or
possibly make another core to do what I need.

Does anyone know of a better core or way to modify one so that the LSB of
the flash data is a separate connection in EDK, so that I can map that pin
solely and not all 16 bits at once?  Also, is there some sort of IO bus
splitter?  I saw that the EDK includes IP cores for a bus splitter, but
they don't accept IO port connections.

I'd be happy to post my MHS and UCF files if that'd help.

Thanks!

Matt

mstanisz <matt.staniszewski@gmail.com> wrote:
 
> I've been working on a Spartan3E Starter Kit and I've hit a snag while
> using both the onboard ADC and the StrataFlash PROM.  The SPI bus MISO
> signal for the ADC and the memory's bit0 for its data are the same net. 
> Could anyone explain how to map the MISO and data pin to the same NET? 
> I've tried doing it in the MHS and UCF files in the Xilinx EDK, but it
> doesn't seem to hold.  I think I may need to either modify the VHDL code or
> possibly make another core to do what I need.

I believe this is explained in the documentation.  It seems that
there are a limited number of I/O pins, and some have two uses.
Page 87 of UG230 explains the problem.  Pretty much, you have
to multiplex between them, so that you can't use both at the
maximum rate.  

-- glen

Hi Glen,

Thanks for the quick response.  I've read through the User's Guide and saw
that part.  I have a GPIO set up for all the CENs and CSs that I need to
control as specified in the documentation.  However, I wasn't sure how to
multiplex the two devices to the N10 net in the EDK, since the flash IP
core specifies a 16-bit bus and I only need to share 1 bit of that with the
MISO signal.  I feel I need to modify the system VHDL file that the EDK
generates, but I wasn't sure where I should do that.  Any help would be
great.  Thanks!

Matt


>mstanisz <matt.staniszewski@gmail.com> wrote:
> 
>> I've been working on a Spartan3E Starter Kit and I've hit a snag while
>> using both the onboard ADC and the StrataFlash PROM.  The SPI bus MISO
>> signal for the ADC and the memory's bit0 for its data are the same net.

>> Could anyone explain how to map the MISO and data pin to the same NET?

>> I've tried doing it in the MHS and UCF files in the Xilinx EDK, but it
>> doesn't seem to hold.  I think I may need to either modify the VHDL
code or
>> possibly make another core to do what I need.
>
>I believe this is explained in the documentation.  It seems that
>there are a limited number of I/O pins, and some have two uses.
>Page 87 of UG230 explains the problem.  Pretty much, you have
>to multiplex between them, so that you can't use both at the
>maximum rate.  
>
>-- glen
>

mstanisz <matt.staniszewski@gmail.com> wrote:
 
> Thanks for the quick response.  I've read through the User's Guide and saw
> that part.  I have a GPIO set up for all the CENs and CSs that I need to
> control as specified in the documentation.  However, I wasn't sure how to
> multiplex the two devices to the N10 net in the EDK, since the flash IP
> core specifies a 16-bit bus and I only need to share 1 bit of that with the
> MISO signal.  I feel I need to modify the system VHDL file that the EDK
> generates, but I wasn't sure where I should do that.  Any help would be
> great.  Thanks!

I am not sure what EDK is.

I think the usual way is to use only one at a time, and make
sure that the other one is disabled.  

There is a similar double use on the LCD display.

-- glen

Hi Glen,

The EDK is Xilinx's Embedded Development Kit.  The way components, such as
the ADC and flash memory, are implemented as reconfigurable Intellectual
Property (IP) cores.  These are essentially reconfigurable blocks of VHDL
code that you set in the GUI.

So, I believe I'll need to modify this VHDL code after it's generated,
since the EDK gui will not let me set a single pin from the flash data bus
to a specific location.  Rather, the IP core only lets you map a 16-bit
bus.

Thanks.

Matt


>mstanisz <matt.staniszewski@gmail.com> wrote:
> 
>> Thanks for the quick response.  I've read through the User's Guide and
saw
>> that part.  I have a GPIO set up for all the CENs and CSs that I need
to
>> control as specified in the documentation.  However, I wasn't sure how
to
>> multiplex the two devices to the N10 net in the EDK, since the flash
IP
>> core specifies a 16-bit bus and I only need to share 1 bit of that with
the
>> MISO signal.  I feel I need to modify the system VHDL file that the
EDK
>> generates, but I wasn't sure where I should do that.  Any help would
be
>> great.  Thanks!
>
>I am not sure what EDK is.
>
>I think the usual way is to use only one at a time, and make
>sure that the other one is disabled.  
>
>There is a similar double use on the LCD display.
>
>-- glen
>

Busses become single pins in the .ucf. Comment out the Data<0> and SPI_MISO 
nets in the ucf so they become internal ports, and add a new NET to 
represent their combined function. You'll need a module to connect and 
select between them. I suspect this is much easier said than done, 
especially if the functions are in different clock domains or if the enables 
are less than dead simple. Also, the added logic might push a marginal 
design beyond timing allowances. All the same, modifying supplied HDL always 
seems a bad idea.


"mstanisz" <matt.staniszewski@gmail.com> wrote in message 
news:1t6dnfigwrwkXmDUnZ2dnUVZ_qmdnZ2d@giganews.com...
> Hi Glen,
>
> The EDK is Xilinx's Embedded Development Kit.  The way components, such as
> the ADC and flash memory, are implemented as reconfigurable Intellectual
> Property (IP) cores.  These are essentially reconfigurable blocks of VHDL
> code that you set in the GUI.
>
> So, I believe I'll need to modify this VHDL code after it's generated,
> since the EDK gui will not let me set a single pin from the flash data bus
> to a specific location.  Rather, the IP core only lets you map a 16-bit
> bus.
>
> Thanks.
>
> Matt
>
>
>>mstanisz <matt.staniszewski@gmail.com> wrote:
>>
>>> Thanks for the quick response.  I've read through the User's Guide and
> saw
>>> that part.  I have a GPIO set up for all the CENs and CSs that I need
> to
>>> control as specified in the documentation.  However, I wasn't sure how
> to
>>> multiplex the two devices to the N10 net in the EDK, since the flash
> IP
>>> core specifies a 16-bit bus and I only need to share 1 bit of that with
> the
>>> MISO signal.  I feel I need to modify the system VHDL file that the
> EDK
>>> generates, but I wasn't sure where I should do that.  Any help would
> be
>>> great.  Thanks!
>>
>>I am not sure what EDK is.
>>
>>I think the usual way is to use only one at a time, and make
>>sure that the other one is disabled.
>>
>>There is a similar double use on the LCD display.
>>
>>-- glen
>> 

Okay, I went ahead and removed the duplicate NETs in the UCF and made them
internal.  I'm trying to figure out how to MUX between the two signals
using a core in EDK.  It does seem like it should be fairly simple, but I'm
not sure how to go about it with IP cores.  Thanks.

Matt

>Busses become single pins in the .ucf. Comment out the Data<0> and
SPI_MISO 
>nets in the ucf so they become internal ports, and add a new NET to 
>represent their combined function. You'll need a module to connect and 
>select between them. I suspect this is much easier said than done, 
>especially if the functions are in different clock domains or if the
enables 
>are less than dead simple. Also, the added logic might push a marginal 
>design beyond timing allowances. All the same, modifying supplied HDL
always 
>seems a bad idea.>
>"mstanisz" <matt.staniszewski@gmail.com> wrote in message 
>news:1t6dnfigwrwkXmDUnZ2dnUVZ_qmdnZ2d@giganews.com...
>> Hi Glen,
>>
>> The EDK is Xilinx's Embedded Development Kit.  The way components, such
as
>> the ADC and flash memory, are implemented as reconfigurable
Intellectual
>> Property (IP) cores.  These are essentially reconfigurable blocks of
VHDL
>> code that you set in the GUI.
>>
>> So, I believe I'll need to modify this VHDL code after it's generated,
>> since the EDK gui will not let me set a single pin from the flash data
bus
>> to a specific location.  Rather, the IP core only lets you map a
16-bit
>> bus.
>>
>> Thanks.
>>
>> Matt
>>
>>
>>>mstanisz <matt.staniszewski@gmail.com> wrote:
>>>
>>>> Thanks for the quick response.  I've read through the User's Guide
and
>> saw
>>>> that part.  I have a GPIO set up for all the CENs and CSs that I
need
>> to
>>>> control as specified in the documentation.  However, I wasn't sure
how
>> to
>>>> multiplex the two devices to the N10 net in the EDK, since the flash
>> IP
>>>> core specifies a 16-bit bus and I only need to share 1 bit of that
with
>> the
>>>> MISO signal.  I feel I need to modify the system VHDL file that the
>> EDK
>>>> generates, but I wasn't sure where I should do that.  Any help would
>> be
>>>> great.  Thanks!
>>>
>>>I am not sure what EDK is.
>>>
>>>I think the usual way is to use only one at a time, and make
>>>sure that the other one is disabled.
>>>
>>>There is a similar double use on the LCD display.
>>>
>>>-- glen
>>> 
>
>

"mstanisz" <matt.staniszewski@gmail.com> wrote in message 
news:19mdndgAN665R2LUnZ2dnUVZ_qadnZ2d@giganews.com...
> Okay, I went ahead and removed the duplicate NETs in the UCF and made them
> internal.  I'm trying to figure out how to MUX between the two signals
> using a core in EDK.  It does seem like it should be fairly simple, but 
> I'm
> not sure how to go about it with IP cores.  Thanks.

Minimally, define a module with OUT pins for the two now disconnected nets, 
additional pins for selection, and an IN pin for the external net. Add the 
external net to the UCF. This is exactly as you would do for any old simple 
design. There might already be an example or usable hdl in the samples files 
for that board.

My normal workflow wraps the EDK project in an ISE project. Instantiate the 
switcher/mux in the top most module, at the same level you instantiate the 
EDK system. Swap and mix the pins as you need. Take a look at (for a project 
named system.xmp) hdl/system_stub.vhd for an example of instantiating the 
EDK system.

I think it would be a bad idea to tear into the pcore hdl or wrappers to do 
this.

The MISO and data<0> signals are bidirectional (IO).  Can you make a
mux/switcher and bus splitter for bidirectional signals?

Matt

>"mstanisz" <matt.staniszewski@gmail.com> wrote in message 
>news:19mdndgAN665R2LUnZ2dnUVZ_qadnZ2d@giganews.com...
>> Okay, I went ahead and removed the duplicate NETs in the UCF and made
them
>> internal.  I'm trying to figure out how to MUX between the two signals
>> using a core in EDK.  It does seem like it should be fairly simple, but

>> I'm
>> not sure how to go about it with IP cores.  Thanks.
>
>Minimally, define a module with OUT pins for the two now disconnected
nets, 
>additional pins for selection, and an IN pin for the external net. Add
the 
>external net to the UCF. This is exactly as you would do for any old
simple 
>design. There might already be an example or usable hdl in the samples
files 
>for that board.
>
>My normal workflow wraps the EDK project in an ISE project. Instantiate
the 
>switcher/mux in the top most module, at the same level you instantiate
the 
>EDK system. Swap and mix the pins as you need. Take a look at (for a
project 
>named system.xmp) hdl/system_stub.vhd for an example of instantiating the

>EDK system.
>
>I think it would be a bad idea to tear into the pcore hdl or wrappers to
do 
>this.
>
>

I've searched a little more and found that if I can somehow merge Ben
Cohen's 0 ohm device
(http://groups.google.com/group/comp.lang.vhdl/msg/7d14832588a0cabb) with
a
bi-directional MUX
(http://www.tek-tips.com/viewthread.cfm?qid=1188582&page=7), then I might
be able to create the VHDL module I would need.  The bus splitting
doesn't
need a module, since in VHDL I'll just manipulate bit0 of the inputted
flash data bus and pass the other 7 bits through.  Would this work? 
Thanks.

Matt

>The MISO and data<0> signals are bidirectional (IO).  Can you make a
>mux/switcher and bus splitter for bidirectional signals?
>
>Matt
>
>>"mstanisz" <matt.staniszewski@gmail.com> wrote in message 
>>news:19mdndgAN665R2LUnZ2dnUVZ_qadnZ2d@giganews.com...
>>> Okay, I went ahead and removed the duplicate NETs in the UCF and made
>them
>>> internal.  I'm trying to figure out how to MUX between the two
signals
>>> using a core in EDK.  It does seem like it should be fairly simple,
but
>
>>> I'm
>>> not sure how to go about it with IP cores.  Thanks.
>>
>>Minimally, define a module with OUT pins for the two now disconnected
>nets, 
>>additional pins for selection, and an IN pin for the external net. Add
>the 
>>external net to the UCF. This is exactly as you would do for any old
>simple 
>>design. There might already be an example or usable hdl in the samples
>files 
>>for that board.
>>
>>My normal workflow wraps the EDK project in an ISE project. Instantiate
>the 
>>switcher/mux in the top most module, at the same level you instantiate
>the 
>>EDK system. Swap and mix the pins as you need. Take a look at (for a
>project 
>>named system.xmp) hdl/system_stub.vhd for an example of instantiating
the
>
>>EDK system.
>>
>>I think it would be a bad idea to tear into the pcore hdl or wrappers
to
>do 
>>this.
>>
>>
>