High-speed signals crossing a split-ground

Hi,

I'm working a design that has isolation between two sub-systems on one
PCB (the grounds are separate).  One side is a "high-speed" digital
side with FPGAs and DDR doing DSP and the other side is an analog side
that has high-resolution 24-bit ADCs and DACs.

I'm planning on using DC-balanced capacitive coupling to move data
back and forth between the two sides.  My concern is at happens when I
AC-couple my signals across cross the split-grounds?  Am I creating
more noise due to the return/image current not having a continuous
return plane?  I have worked out both single-ended AC-coupling and
schemes using LVDS/CML.

The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall
times.

The isolation is due partially to safety and to keep as much noise
away from analog side as I can.  I haven't found much literature on
isolation and crossing split-grounds.

Your opinions are welcome.

On May 4, 2:06=A0pm, ee_ether <xjjzdv...@sneakemail.com> wrote:
> Hi,
>
> I'm working a design that has isolation between two sub-systems on one
> PCB (the grounds are separate). =A0One side is a "high-speed" digital
> side with FPGAs and DDR doing DSP and the other side is an analog side
> that has high-resolution 24-bit ADCs and DACs.
>
> I'm planning on using DC-balanced capacitive coupling to move data
> back and forth between the two sides. =A0My concern is at happens when I
> AC-couple my signals across cross the split-grounds? =A0Am I creating
> more noise due to the return/image current not having a continuous
> return plane? =A0I have worked out both single-ended AC-coupling and
> schemes using LVDS/CML.
>
> The capacitively coupled signals are <=3D 75 MHz, with 5 ns rise/fall
> times.
>
> The isolation is due partially to safety and to keep as much noise
> away from analog side as I can. =A0I haven't found much literature on
> isolation and crossing split-grounds.
>
> Your opinions are welcome.

Sounds like you are rolling your own?

Might be smarter/easier to look at Analog Devices Digital Isolators ?

-jg

Isolation for safety purposes should probably be done in front of the ADC. 
In most other cases splitting ground creates more problems than it solves. 
If you can show that you need roughly more than 60 dB of isolation between 
your circuits then you might need to resort to splitting grounds, but you 
need to know what you are doing very well. AC coupled or not return currents 
will still want to travel through the plane, so you can only split it under 
the chip. The best resource for discussions on this topic is the Signal 
Integrity mailing list. The SI-List archive can be found at 
http://www.freelists.org/archive/si-list/.

/Mikhail




"ee_ether" <xjjzdv402@sneakemail.com> wrote in message 
news:707a89a7-c3cf-4953-b776-b5d36265f5b4@r13g2000vbr.googlegroups.com...
> Hi,
>
> I'm working a design that has isolation between two sub-systems on one
> PCB (the grounds are separate).  One side is a "high-speed" digital
> side with FPGAs and DDR doing DSP and the other side is an analog side
> that has high-resolution 24-bit ADCs and DACs.
>
> I'm planning on using DC-balanced capacitive coupling to move data
> back and forth between the two sides.  My concern is at happens when I
> AC-couple my signals across cross the split-grounds?  Am I creating
> more noise due to the return/image current not having a continuous
> return plane?  I have worked out both single-ended AC-coupling and
> schemes using LVDS/CML.
>
> The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall
> times.
>
> The isolation is due partially to safety and to keep as much noise
> away from analog side as I can.  I haven't found much literature on
> isolation and crossing split-grounds.
>
> Your opinions are welcome. 

ee_ether wrote:
> Hi,
> 
> I'm working a design that has isolation between two sub-systems on one
> PCB (the grounds are separate).  One side is a "high-speed" digital
> side with FPGAs and DDR doing DSP and the other side is an analog side
> that has high-resolution 24-bit ADCs and DACs.
> 
> I'm planning on using DC-balanced capacitive coupling to move data
> back and forth between the two sides.  My concern is at happens when I
> AC-couple my signals across cross the split-grounds?  Am I creating
> more noise due to the return/image current not having a continuous
> return plane?  I have worked out both single-ended AC-coupling and
> schemes using LVDS/CML.
> 
> The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall
> times.
> 
> The isolation is due partially to safety and to keep as much noise
> away from analog side as I can.  I haven't found much literature on
> isolation and crossing split-grounds.
> 
> Your opinions are welcome.

Are you sure that split ground planes would really help?  Think about 
the layout of your board, and the way current on the ground plane would 
flow.  DC ground currents aim to follow a direct path on the ground 
plane, and high frequency currents aim to minimize the current loop area 
(i.e., minimal impedance in both cases).  If the ground currents created 
by the digital logic are flowing around the digital parts, there is no 
reason they should wander off under the analogue parts to cause noise there.

(That's my understanding of the theory - I've not worked on any high 
frequency, high sensitivity analogue boards in practice.)

In comp.arch.fpga MM <mbmsv@yahoo.com> wrote:

> Isolation for safety purposes should probably be done in front of the ADC. 
> In most other cases splitting ground creates more problems than it solves. 
> If you can show that you need roughly more than 60 dB of isolation between 

The OP mentioned a 24 bit ADC, which suggests much more than
60dB is needed.  

> your circuits then you might need to resort to splitting grounds, but you 
> need to know what you are doing very well. AC coupled or not return currents 
> will still want to travel through the plane, so you can only split it under 
> the chip. 

If it is differential shouldn't it be mostly balanced?

(snip)

-- glen

-jg wrote:
> On May 4, 2:06 pm, ee_ether <xjjzdv...@sneakemail.com> wrote:
>> Hi,
>>
>> I'm working a design that has isolation between two sub-systems on one
>> PCB (the grounds are separate).  One side is a "high-speed" digital
>> side with FPGAs and DDR doing DSP and the other side is an analog side
>> that has high-resolution 24-bit ADCs and DACs.
>>
>> I'm planning on using DC-balanced capacitive coupling to move data
>> back and forth between the two sides.  My concern is at happens when I
>> AC-couple my signals across cross the split-grounds?  Am I creating
>> more noise due to the return/image current not having a continuous
>> return plane?  I have worked out both single-ended AC-coupling and
>> schemes using LVDS/CML.
>>
>> The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall
>> times.
>>
>> The isolation is due partially to safety and to keep as much noise
>> away from analog side as I can.  I haven't found much literature on
>> isolation and crossing split-grounds.
>>
>> Your opinions are welcome.
> 
> Sounds like you are rolling your own?
> 
> Might be smarter/easier to look at Analog Devices Digital Isolators ?
> 
> -jg
> 
> 

I agree with jg - the AD parts are worth looking into.  They're not that 
expensive, and they've been tested to international standards for high 
voltage isolation.  That will help with agency certification, assuming 
that your product requires it.

Chris

On May 3, 7:06=A0pm, ee_ether <xjjzdv...@sneakemail.com> wrote:
> Hi,
>
> I'm working a design that has isolation between two sub-systems on one
> PCB (the grounds are separate). =A0One side is a "high-speed" digital
> side with FPGAs and DDR doing DSP and the other side is an analog side
> that has high-resolution 24-bit ADCs and DACs.
>
> I'm planning on using DC-balanced capacitive coupling to move data
> back and forth between the two sides. =A0My concern is at happens when I
> AC-couple my signals across cross the split-grounds? =A0Am I creating
> more noise due to the return/image current not having a continuous
> return plane? =A0I have worked out both single-ended AC-coupling and
> schemes using LVDS/CML.
>
> The capacitively coupled signals are <=3D 75 MHz, with 5 ns rise/fall
> times.
>
> The isolation is due partially to safety and to keep as much noise
> away from analog side as I can. =A0I haven't found much literature on
> isolation and crossing split-grounds.
>
> Your opinions are welcome.

My experiences have shown:

You can probably run data lines single-ended, with series resistors to
slow the edges and limit the current.  You are right about the long
return current path causing radiated noise, but the random nature of
the data lines will make it rather spread-spectrum, so it should be
tolerable.  Clocks, on the other hand, should only cross a split-plane
as differential signals.  You still get radiated emissions, but much
less.  The diff pair over split plane can be modeled as a diff pair
over continuous plane plus a small loop antenna with dimensions equal
to the split width and the pair spacing.  So make the split small and
the lvds traces close together.  Henry Ott covered this in one of his
books; sorry I don't remember which one.

Barry

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message 
news:gtm4pd$fa6$1@naig.caltech.edu...
>
> The OP mentioned a 24 bit ADC, which suggests much more than
> 60dB is needed.
>

Glen,

I noticed this fact, but taken out of the context of application it doesn't 
necessarily mean anything.

> If it is differential shouldn't it be mostly balanced?

Balanced doesn't mean that return current for one side actually uses another 
side.


/Mikhail 

In comp.arch.fpga MM <mbmsv@yahoo.com> wrote:

(snip)
 
> I noticed this fact, but taken out of the context of 
> application it doesn't necessarily mean anything.

(after I wrote) 
>> If it is differential shouldn't it be mostly balanced?
 
> Balanced doesn't mean that return current for one side actually 
> uses another side.

I qualified with "mostly".  One would have to look at the
individual case.  Properly terminated, it is hard to see whereelse
the current would go, but signals aren't always properly terminated.

-- glen

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message 
news:gtncrq$1a8$2@naig.caltech.edu...
>
> (after I wrote)
>>> If it is differential shouldn't it be mostly balanced?
>
>> Balanced doesn't mean that return current for one side actually
>> uses another side.
>
> I qualified with "mostly".  One would have to look at the
> individual case.  Properly terminated, it is hard to see whereelse
> the current would go, but signals aren't always properly terminated.

Please check out this article by Eric Bogatin:
http://www.thefreelibrary.com/So+far,+so+close:+understanding+return+current+in+a+differential...-a0103123486

It should be available on his web site (http://www.bethesignal.net/) as well 
in a better format but I couldn't find it quickly...


/Mikhail