[newbie asking] I don't like Xilinx

I got used to Altera, but now I have to launch a big project in Xilinx
Virtex.

My problem which I encountered today is that message:

ERROR:Pack:1107 - Unable to combine the following symbols into a
single IOB
   component:
   	PAD symbol "clk200_n" (Pad Signal = clk200_n)
   	SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/
SLAVEBUF.DIFFIN" (Output
   Signal = u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN)
   An IO component of type IOB was chosen because the IO contains
symbols and/or
   properties consistent with input, output, or bi-directional usage
and
   contains no other symbols or properties that require a more
specific IO
   component type.
   Each of the following constraints specifies an illegal physical
site for a
   component of type IOB:
   	Symbol "clk200_n" (LOC=C8 [Physical Site Type = IPAD])
   The component type is determined by the types of logic and the
properties and
   configuration of the logic it contains. Please double check that
the types of
   logic elements and all of their relevant properties and
configuration options
   are compatible with the physical site type of the constraint.
   Please correct the constraints accordingly.

More or less, I understand the problem. Some important information is
missing in my UCF file, which I prepared, but incorrectly. Please help
me. What should I do to "correct the constraints accordingly"?

On 12 Mai, 15:06, Marteno Rodia <marteno_ro...@o2.pl> wrote:
> I got used to Altera, but now I have to launch a big project in Xilinx
> Virtex.
>
> My problem which I encountered today is that message:
>
> ERROR:Pack:1107 - Unable to combine the following symbols into a
> single IOB
> =A0 =A0component:
> =A0 =A0 =A0 =A0 PAD symbol "clk200_n" (Pad Signal =3D clk200_n)
> =A0 =A0 =A0 =A0 SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/
> SLAVEBUF.DIFFIN" (Output
> =A0 =A0Signal =3D u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN)
> =A0 =A0An IO component of type IOB was chosen because the IO contains
> symbols and/or
> =A0 =A0properties consistent with input, output, or bi-directional usage
> and
> =A0 =A0contains no other symbols or properties that require a more
> specific IO
> =A0 =A0component type.
> =A0 =A0Each of the following constraints specifies an illegal physical
> site for a
> =A0 =A0component of type IOB:
> =A0 =A0 =A0 =A0 Symbol "clk200_n" (LOC=3DC8 [Physical Site Type =3D IPAD]=
)
> =A0 =A0The component type is determined by the types of logic and the
> properties and
> =A0 =A0configuration of the logic it contains. Please double check that
> the types of
> =A0 =A0logic elements and all of their relevant properties and
> configuration options
> =A0 =A0are compatible with the physical site type of the constraint.
> =A0 =A0Please correct the constraints accordingly.
>
> More or less, I understand the problem. Some important information is
> missing in my UCF file, which I prepared, but incorrectly. Please help
> me. What should I do to "correct the constraints accordingly"?

Hi Marteno,
looks like you want to use a differential clock Input (clk200_n) but
you have placed it on a pad that has no such input (for clock signals)
connected to it.
Take a closer look at the datasheet for the  locations of global clock
inputs and their corresponding differential inputs.

 Have a nice synthesis
  Eilert

On Tue, 12 May 2009 06:06:42 -0700 (PDT), Marteno Rodia
<marteno_rodia@o2.pl> wrote:

>ERROR:Pack:1107 - Unable to combine the following symbols into a
>single IOB
>   component:
>   	PAD symbol "clk200_n" (Pad Signal = clk200_n)
>   	SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/
...
>More or less, I understand the problem. Some important information is
>missing in my UCF file, which I prepared, but incorrectly. Please help
>me. What should I do to "correct the constraints accordingly"?

By looking at your name of the pad (and assuming there is a clk200_p)
I'm assuming you want differential IO. If that's the case you need to
add a property to your UCF file marking them so ie LVPECL etc.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

On May 12, 5:21 pm, Muzaffer Kal <k...@dspia.com> wrote:
> By looking at your name of the pad (and assuming there is a clk200_p)
> I'm assuming you want differential IO. If that's the case you need to
> add a property to your UCF file marking them so ie LVPECL etc.

All, thank you for your answers. Yes, I'm using differential clock
signals. I've checked also the pins once more, they're correct. I
incline to thinking that there's an important constraint in the UCF
file missing. The problem is I don't know the constraint which needs
to be added (I'm not very familiar with Xilinx yet).
In the UCF file I have specified the NET-LOC constraints as well as
IOSTANDARD definition. For clock inputs I used LVPECL_25:

NET  "clk200_n" IOSTANDARD = LVPECL_25;

Then, I added DIFF_TERM (please, don't ask why, I've found in Google):

NET  "clk200_n" IOSTANDARD = LVPECL_25 | DIFF_TERM = TRUE;

The result is the same as before (identical error message). If it can
help, the Target Device is xc5vsx95t (Virtex-5 family).

MR :/

Did you add the correct buffer from the Xilinx Unisim library to your
HDL code? As you are using a differential signal/LVPECL standard you
should add the ibufgds_lvpecl_25 to the HDL code and connect it to the
clk_200 signals.

Devas


-- 
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------------------------------------------------------------------------
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View this thread: http://www.fpgacentral.com/group/showthread.php?t=90004

I've encoutered the aforementioned error while compiling not my own
code, but code obtained from Core Generator, in which I made some
modifications... The code seems to use the unisim library.

MR

On Wed, 13 May 2009 00:17:32 -0700 (PDT), Marteno Rodia
<marteno_rodia@o2.pl> wrote:

>On May 12, 5:21 pm, Muzaffer Kal <k...@dspia.com> wrote:
>> By looking at your name of the pad (and assuming there is a clk200_p)
>> I'm assuming you want differential IO. If that's the case you need to
>> add a property to your UCF file marking them so ie LVPECL etc.
>
>All, thank you for your answers. Yes, I'm using differential clock
>signals. I've checked also the pins once more, they're correct. I
>incline to thinking that there's an important constraint in the UCF
>file missing. The problem is I don't know the constraint which needs
>to be added (I'm not very familiar with Xilinx yet).
>In the UCF file I have specified the NET-LOC constraints as well as
>IOSTANDARD definition. For clock inputs I used LVPECL_25:
>
>NET  "clk200_n" IOSTANDARD = LVPECL_25;
>
>Then, I added DIFF_TERM (please, don't ask why, I've found in Google):
>
>NET  "clk200_n" IOSTANDARD = LVPECL_25 | DIFF_TERM = TRUE;
>
>The result is the same as before (identical error message). If it can
>help, the Target Device is xc5vsx95t (Virtex-5 family).
>
>MR :/

Which device are you using and which IOs are you trying to use? Also
how are you instantiating the IO pad(s) (and the associated BUFG)?
Please show those 2/3 lines here.

On May 12, 8:06=A0am, Marteno Rodia <marteno_ro...@o2.pl> wrote:
> I got used to Altera, but now I have to launch a big project in Xilinx
> Virtex.
>
> My problem which I encountered today is that message:
>
> ERROR:Pack:1107 - Unable to combine the following symbols into a
> single IOB
> =A0 =A0component:
> =A0 =A0 =A0 =A0 PAD symbol "clk200_n" (Pad Signal =3D clk200_n)
> =A0 =A0 =A0 =A0 SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/
> SLAVEBUF.DIFFIN" (Output
> =A0 =A0Signal =3D u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN)
> =A0 =A0An IO component of type IOB was chosen because the IO contains
> symbols and/or
> =A0 =A0properties consistent with input, output, or bi-directional usage
> and
> =A0 =A0contains no other symbols or properties that require a more
> specific IO
> =A0 =A0component type.
> =A0 =A0Each of the following constraints specifies an illegal physical
> site for a
> =A0 =A0component of type IOB:
> =A0 =A0 =A0 =A0 Symbol "clk200_n" (LOC=3DC8 [Physical Site Type =3D IPAD]=
)
> =A0 =A0The component type is determined by the types of logic and the
> properties and
> =A0 =A0configuration of the logic it contains. Please double check that
> the types of
> =A0 =A0logic elements and all of their relevant properties and
> configuration options
> =A0 =A0are compatible with the physical site type of the constraint.
> =A0 =A0Please correct the constraints accordingly.
>
> More or less, I understand the problem. Some important information is
> missing in my UCF file, which I prepared, but incorrectly. Please help
> me. What should I do to "correct the constraints accordingly"?

Please explain how you understand the problem as you mentioned above

Marteno Rodia skrev:
> I got used to Altera, but now I have to launch a big project in Xilinx
> Virtex.
> 
> My problem which I encountered today is that message:
> 
> ERROR:Pack:1107 - Unable to combine the following symbols into a
> single IOB
>    component:
>    	PAD symbol "clk200_n" (Pad Signal = clk200_n)
>    	SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/
> SLAVEBUF.DIFFIN" (Output
>    Signal = u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN)
>    An IO component of type IOB was chosen because the IO contains
> symbols and/or
>    properties consistent with input, output, or bi-directional usage
> and
>    contains no other symbols or properties that require a more
> specific IO
>    component type.
>    Each of the following constraints specifies an illegal physical
> site for a
>    component of type IOB:
>    	Symbol "clk200_n" (LOC=C8 [Physical Site Type = IPAD])
>    The component type is determined by the types of logic and the
> properties and
>    configuration of the logic it contains. Please double check that
> the types of
>    logic elements and all of their relevant properties and
> configuration options
>    are compatible with the physical site type of the constraint.
>    Please correct the constraints accordingly.
> 
> More or less, I understand the problem. Some important information is
> missing in my UCF file, which I prepared, but incorrectly. Please help
> me. What should I do to "correct the constraints accordingly"?

It sound to mee that one fo the followig could be the reason for the 
trouble:

1. clk200_n and clk200_p are not placed at _N and _P type pins check 
pinout table for you package
2. The logic standard is not supported in bank where the pins are 
located, check that the VCCIO voltage support the standards you use in 
that bank
3. An identical pin location is already used elsewhere
4. More deeper placement trouble.. ??

Yes there's a lot of details to know about when using FPGAs, but it's 
nothing different from Altera or other FPGA companies.. So just keep 
reading the datasheets and user guides...

Good luck

Finn Nielsen
www.morphologic.dk

> Which device are you using and which IOs are you trying to use?

I'm to use the Virtex-5 LXT/SXT PCI Expres board the AES-XLX-V5SXT-
PCIE95-G circuit. There are 4 clock signals and I'm using following
pins (according to the board documentation):

sys_clk_p - E4
sys_clk_n - D4
sys_clk_p - D8
sys_clk_n - C8

> Please explain how you understand the problem as you mentioned above

Besides the VHDL code, Xilinx ISE needs an additional file in a
proprietary format (UCF). I think the problem is I don't know how to
specify all the necessary constraints in the file (lack of experience
with Xilinx).

MR