FPGA/DSP system design problem

Dear All:

I am thinking about my system, the picture is here:

http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/

I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.

Two choices:

1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-

>DPRAM

2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
DSP works as a coprocessor.
In choice 2, the USB could also connect from DSP but this will
accelerate processed data transfer, decelerate the raw data transfer.

Other questions:

I also need to store raw data, thus the data saving path will be
different:
Choice 1: the raw data will be from ADC -> DSP -> FLASH
Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash
good for fast data saving, or use EEPROM instead?)

It will meet the same question when I save processed data on board.

The last question is FIFO vs. DPRAM, FIFO could be implemented in
FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
flexibility for sure.

Thanks!

I honestly can't understand exactly what you are trying to do.  Your
description may be clear to you, but I don't understand the details.
From the drawing, it does appear that you want to move data from an
image sensor via ADC to either/or the FPGA and DSP, do some processing
and then dump the data to the USB port.  I'm not clear on whether this
needs to be live or it is an image capture like a camera.

The only thing I can say is that sharing the perpherial devices, (USB,
SDRAM and flash) is not as easy as putting each device on one or the
other processor (FPGA or DSP).  Trying to share a high speed bus is
not so easy to do from a signal integrity standpoint.

Your diagram does not show what the dual port ram is connected to on
the other port.  I guess this is something else outside the diagram?
Yes, if you don't need a lot of dual port ram, you can use the ram
internal to the FPGA (for most FPGAs).

Rick


On May 13, 5:13=A0pm, bigca...@gmail.com wrote:
> Dear All:
>
> I am thinking about my system, the picture is here:
>
> http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/
>
> I want to transfer the raw/processed image sensor data to USB 2.0 or
> dpram.
>
> Two choices:
>
> 1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-
>
> >DPRAM
>
> 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
> EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
> DSP works as a coprocessor.
> In choice 2, the USB could also connect from DSP but this will
> accelerate processed data transfer, decelerate the raw data transfer.
>
> Other questions:
>
> I also need to store raw data, thus the data saving path will be
> different:
> Choice 1: the raw data will be from ADC -> DSP -> FLASH
> Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash
> good for fast data saving, or use EEPROM instead?)
>
> It will meet the same question when I save processed data on board.
>
> The last question is FIFO vs. DPRAM, FIFO could be implemented in
> FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
> flexibility for sure.
>
> Thanks!

On May 13, 10:13=A0pm, bigca...@gmail.com wrote:
> Dear All:
>
> I am thinking about my system, the picture is here:
>
> http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/
>
> I want to transfer the raw/processed image sensor data to USB 2.0 or
> dpram.
>
> Two choices:
>
> 1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-
>
> >DPRAM
>
> 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
> EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
> DSP works as a coprocessor.
> In choice 2, the USB could also connect from DSP but this will
> accelerate processed data transfer, decelerate the raw data transfer.

What kind of processing do you need to do?
If you are mostly concerned with taking in the camera data, fpga is
certainly faster. It is also faster than dsp for the processing where
algorithms have parallelisms in them.
It also depends on your preference in implementing algorithms in
hardware or software.
>
> Other questions:
>
> I also need to store raw data, thus the data saving path will be
> different:
> Choice 1: the raw data will be from ADC -> DSP -> FLASH
> Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash
> good for fast data saving, or use EEPROM instead?)

How much of the data you need to store.
>
> It will meet the same question when I save processed data on board.
>
> The last question is FIFO vs. DPRAM, FIFO could be implemented in
> FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
> flexibility for sure.
>
> Thanks!

On May 13, 10:13=A0pm, bigca...@gmail.com wrote:
> Dear All:
>
> I am thinking about my system, the picture is here:
>
> http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/
>
> I want to transfer the raw/processed image sensor data to USB 2.0 or
> dpram.
>
> Two choices:
>
> 1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
> USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-
>
> >DPRAM
>
> 2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
> EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
> DSP works as a coprocessor.
> In choice 2, the USB could also connect from DSP but this will
> accelerate processed data transfer, decelerate the raw data transfer.
>
> Other questions:
>
> I also need to store raw data, thus the data saving path will be
> different:
> Choice 1: the raw data will be from ADC -> DSP -> FLASH
> Choice 2: the raw data will be from ADC -> FPGA -> FLASH (Is Flash
> good for fast data saving, or use EEPROM instead?)
>
> It will meet the same question when I save processed data on board.
>
> The last question is FIFO vs. DPRAM, FIFO could be implemented in
> FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
> flexibility for sure.
>
> Thanks!

It would be easier to interface your ADC channel(s) to the FPGA. You
could then capture the data in your FPGA and store the samples or
frames to an external memory like SDRAM/ZBT SRAM (to offer a larger
storage capacity than FIFO/DPRAM). It would be relatively easy to
implement your ADC control in the FPGA.
Then your FPGA would be connected to the EMIF_A, and the DSP would
access the FPGA like an external "memory device". You can have a look
at the Xilinx application note XAPP753:
http://www.xilinx.com/support/documentation/application_notes/xapp753.pdf
Your DSP would ideally have a dedicated bank of SDRAM, and also be
connected to the Flash memory that would be used to store your DSP
bootloader, FPGA bitstream and even your application. This would allow
you to have a standalone system if required and it may also be
possible to store some user data in Flash. However, I would recommend
to use a microSD socket/Flash if you wish to store some of your data,
or directly use the external memory devices attached to the DSP and
the FPGA since they may be faster and give you better performance.
You could use a USB chip directly interface to the DSP, and then
transfer data fast. But you may not reach more than 20-40MB/s using a
USB. If your application requires a faster throughput ot the host, you
may have to consider PCI/PCI-64 or similar systems.

Such solutions exist off the shelf from COTS hardware vendors. I would
recommend that you have a look at the exisiting solutions before
starting such a design.

- Sebatsien
www.sundance.com