Open source processors

Hi,

I'm trying to find an open source processor as a basis for a research,
preferably it is in VHDL and implements a 5-stage RISC pipeline with
bypassing (exceptions are not a concern), of course if you know of any
processor with a clean 5-stage pipeline with bypassing, please let me
know. It would be awesome if it implements the MIPS ISA.

I've tried the open cores website, and have looked at 2 MIPS ISA
implementations: Plasma and miniMIPS.
Problem is Plasma does not deal with bypassing and is not a 5-stage
pipeline, and miniMIPS is rather weird, it process instructions every
other cycle, so it would process, then it would pause everything on
the next cycle.

So I'm wondering maybe there would be someone out there on the
internets that know about this, please help me out :) Thanks!

Regards,
David.

On May 14, 3:29=A0am, DH <dh1...@gmail.com> wrote:
> Hi,
>
> I'm trying to find an open source processor as a basis for a research,
> preferably it is in VHDL and implements a 5-stage RISC pipeline with
> bypassing (exceptions are not a concern), of course if you know of any
> processor with a clean 5-stage pipeline with bypassing, please let me
> know. It would be awesome if it implements the MIPS ISA.
>
> I've tried the open cores website, and have looked at 2 MIPS ISA
> implementations: Plasma and miniMIPS.
> Problem is Plasma does not deal with bypassing and is not a 5-stage
> pipeline, and miniMIPS is rather weird, it process instructions every
> other cycle, so it would process, then it would pause everything on
> the next cycle.
>
> So I'm wondering maybe there would be someone out there on the
> internets that know about this, please help me out :) Thanks!
>
> Regards,
> David.

try also

http://yari.thorn.ws/YARI/Introduction.html

it is now useable for Xilinx too, (prev versions only compiled with
quartus)

Antti

On 14 May, 01:29, DH <dh1...@gmail.com> wrote:
> Hi,
>
> I'm trying to find an open source processor as a basis for a research,
> preferably it is in VHDL and implements a 5-stage RISC pipeline with
> bypassing (exceptions are not a concern), of course if you know of any
> processor with a clean 5-stage pipeline with bypassing, please let me
> know. It would be awesome if it implements the MIPS ISA.
>
> I've tried the open cores website, and have looked at 2 MIPS ISA
> implementations: Plasma and miniMIPS.
> Problem is Plasma does not deal with bypassing and is not a 5-stage
> pipeline, and miniMIPS is rather weird, it process instructions every
> other cycle, so it would process, then it would pause everything on
> the next cycle.
>
> So I'm wondering maybe there would be someone out there on the
> internets that know about this, please help me out :) Thanks!
>
> Regards,
> David.

Have a look at Lattice Mico32. It's in verilog rather than VHDL, and
not MIPS, but is quite similar and is pipelined with bypassing.

http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm

Cheers,
Jon

On May 13, 7:29=A0pm, DH <dh1...@gmail.com> wrote:
> Hi,
>
> I'm trying to find an open source processor as a basis for a research,
> preferably it is in VHDL and implements a 5-stage RISC pipeline with
> bypassing (exceptions are not a concern), of course if you know of any
> processor with a clean 5-stage pipeline with bypassing, please let me
> know. It would be awesome if it implements the MIPS ISA.
>
> I've tried the open cores website, and have looked at 2 MIPS ISA
> implementations: Plasma and miniMIPS.
> Problem is Plasma does not deal with bypassing and is not a 5-stage
> pipeline, and miniMIPS is rather weird, it process instructions every
> other cycle, so it would process, then it would pause everything on
> the next cycle.
>
> So I'm wondering maybe there would be someone out there on the
> internets that know about this, please help me out :) Thanks!
>
> Regards,
> David.

Why the specific requirements?  What is the research focusing on?

DH;476369 Wrote: 
> Hi,
> 
> I'm trying to find an open source processor as a basis for a research,
> preferably it is in VHDL and implements a 5-stage RISC pipeline with
> bypassing (exceptions are not a concern), of course if you know of any
> processor with a clean 5-stage pipeline with bypassing, please let me
> know. It would be awesome if it implements the MIPS ISA.
> 
> I've tried the open cores website, and have looked at 2 MIPS ISA
> implementations: Plasma and miniMIPS.
> Problem is Plasma does not deal with bypassing and is not a 5-stage
> pipeline, and miniMIPS is rather weird, it process instructions every
> other cycle, so it would process, then it would pause everything on
> the next cycle.
> 
> So I'm wondering maybe there would be someone out there on the
> internets that know about this, please help me out :) Thanks!
> 
> Regards,
> David.

Have you considered LEON.
I used for some self learing projects:
Improving The LEON2-XST PCI Interface
'VHDL, verilog, design, verification, scripts, ...'
(http://bknpk.no-ip.biz/LEON/leon_1.html)
I2C master connected and tested with LEON Processor
'VHDL, verilog, design, verification, scripts, ...'
(http://bknpk.no-ip.biz/I2C/leon_2.html)
...


-- 
pini_1234
------------------------------------------------------------------------
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View this thread: http://www.fpgacentral.com/group/showthread.php?t=90062

<'use_real_email'> wrote in message 
news:pini_1234.3s8qh5@noemail.example.com...
> Have you considered LEON.
> I used for some self learing projects:
> Improving The LEON2-XST PCI Interface
> 'VHDL, verilog, design, verification, scripts, ...'
> (http://bknpk.no-ip.biz/LEON/leon_1.html)

You must be color blind in a different way than I am. :D Uggh! My eyes are 
squirting blood, and I still couldn't read the links.

Hi, thanks to everyone that replied to this post! I really appreciate
it.

To Antti: Thanks, the YARI processor looks like a good processor.

To Jon: Thanks, I will look at it when I run out of VHDL options :)

To Chris: The requirement is because I have done my analysis based on
a 5 stage pipelined MIPS (by hand...), so I'm trying not to have to
redo it for a different instruction set, and I understand its pipeline
structure quite well from texts like Hennessy & Patterson. It is quite
an arbitrary choice. Also I think I found a tool (CoWare) that will
make life a lot simpler :)

To pini_1234 & MikeWhy: Thanks. I looked at LEON before, but was
turned off by the relatively complex project organisation (says about
90 files on wiki), it is certainly very good vehicle for
experimentation if I have the time :)

Update: After some discussion at school, I'm going
to use the CoWare processor designer at school to make my processor
now, it provides a reference 5 stage pipelined RISC core with
bypassing done already, it's not MIPS, but there's compiler/assembler/
linker available. The best thing about this tool (though may be hard
to do, we'll see) is that you can use it to generate the tool chain
along with the processor RTL code. I will fall back to good old VHDL
if this tool doesn't deliver, thanks to everyone that replied to this
post!

On May 18, 5:06=A0pm, DH <dh1...@gmail.com> wrote:
> Hi, thanks to everyone that replied to this post! I really appreciate
> it.
>
> To Antti: Thanks, the YARI processor looks like a good processor.

Why thank you :-)

> Update: After some discussion at school, I'm going
> to use the CoWare processor designer at school to make my processor
> now, it provides a reference 5 stage pipelined RISC core with
> bypassing done already, it's not MIPS, but there's compiler/assembler/
> linker available. The best thing about this tool (though may be hard
> to do, we'll see) is that you can use it to generate the tool chain
> along with the processor RTL code. I will fall back to good old VHDL
> if this tool doesn't deliver, thanks to everyone that replied to this
> post!

Good luck with that. If you change your mind and want to give YARI a
spin, I can help you.

It might be useful to know how your core will be used. Fx. will it be
backed up with external memory or used as an embedded processor using
only the FPGA provided memory blocks? Which parts of the processor are
you planning on experimenting with?

Cheers,
Tommy

Though I was familiar with Chuck Thacker's (designer of the Xerox Alto
and Microsoft TabletPC) simple FPGA processor, I didn't know it was
documented anywhere until a friend sent me this link a couple of days
ago:

http://www.bottomup.co.nz/mirror/Thacker-A_Tiny_Computer-3.pdf

This paper includes the Verilog sources. As it is, it reminds me of a
fat 32 bit version of Picoblaze but it is trivial to implement some of
the expansions that are suggested.

-- Jecel

On May 21, 9:53=A0am, Jecel <je...@merlintec.com> wrote:

# http://www.bottomup.co.nz/mirror/Thacker-A_Tiny_Computer-3.pdf

Nice, I like the 'fat' register area, as that is one area FPGAs have
almost for free.

I also see the extension notes to allow multiple contexts, or virtual
cores, which
is another natural extension from the BRAMs

["
The second extension addresses the lack of interrupts. Since the BRAM
holding the
registers can hold eight full register contexts, it should be
straightforward to provide a
mechanism similar to that of the Alto. A separate three-bit Context
register would hold
the current context. Saving and restoring the current context=92s PC on
a task switch is a bit problematic, but it is probably fairly
straightforward."]

This could, of course, map to more than 8, with a simple ROM if you
only needed a smaller register array for some contexts. (eg 4 x 128R
cores, and 16 x 32R cores)

-jg