On 2009-05-14, acd <acd4usenet@lycos.de> wrote:> I think this second step should be easily doable with XSLT if the > netlist is represented as XML. > I wonder if there are existing formats and tools to do this.I would look at the kind of formats that commercial synthesis tools output. This is most likely going to be some sort of EDIF based format. I know that Precision outputs EDIF files when synthesizing to Xilinx and I guess that other vendors' backend tools can handle EDIF inputs as well. Another choice if you are targetting Xilinx is XDL, although that is a bit more low level (you will have to map LUTs into slices before you can use XDL). /Andreas
Re: XML for LUT+FF netlist representation in (academic) tools
Started by ●May 14, 2009
Reply by ●May 14, 20092009-05-14
Hi, I am currently working on a circuit generator problem, which I also want to target to FPGAs. However, I want to make my tools somewhat technology/vendor independent by generating a netlist of LUT's and FlipFlops. This means my tool would be configured with the available LUT sizes and area costs. A second step should then translate the netlist into a technology- specific form. I think this second step should be easily doable with XSLT if the netlist is represented as XML. I wonder if there are existing formats and tools to do this. I have found individual academic projects that do something similar, but none seemed to have reached a wider scope. Is there a wide-spread approach? Currently I target ASIC technologies and generate VHDL. If I give this VHDL for instance to ISE, it runs for hours and I am not convinced that the result is close to what I intend. The reason is that this VHDL shares signals on a gate level. So the FPGA mapper has a hard time to figure out which gates need to be replicated and put together with other gates into a LUT. Regards, Andreas
Reply by ●May 14, 20092009-05-14
On Wed, 13 May 2009 23:14:41 -0700 (PDT), acd <acd4usenet@lycos.de> wrote:>Hi, > >I am currently working on a circuit generator problem, which I also >want to target to FPGAs. >However, I want to make my tools somewhat technology/vendor >independent by generating a netlist of LUT's and >FlipFlops. This means my tool would be configured with the available >LUT sizes and area costs. >A second step should then translate the netlist into a technology- >specific form....>Currently I target ASIC technologies and generate VHDL. >If I give this VHDL for instance to ISE, it runs for hours and I am >not convinced that the result is close to what I intend. >The reason is that this VHDL shares signals on a gate level. So the >FPGA mapper has a hard time to figure out which gates need to be >replicated and put together with other gates into a LUT.It sounds as if your tool has a good idea what to replicate and how to optimally map it. You could consider adding this information to the VHDL in the form of attributes - e.g. "keep" and "RLOC" when targetting Xilinx; others for other technologies; probably at the second tech-specific stage. Search online for "Death of the RLOC?" to see this in action. Be prepared for a tussle with ISE to overcome its optimisations... - Brian